SiC Device Impurity Regions Reduce Drain-Gate Capacitance

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Solution Overview

Problem

Existing silicon carbide semiconductor devices face challenges in reducing electrostatic capacitance between the drain and gate electrodes, which affects switching characteristics, and there is a need for improved impurity region configurations to enhance conductivity and reduce parasitic capacitance.

Innovation Solution

The silicon carbide semiconductor device incorporates specific impurity regions with defined conductivity types and concentrations, located between the gate pad and drain electrode, including a second impurity region electrically connected to the source electrode, to effectively reduce electrostatic capacitance and improve switching characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If conventional impurity region configurations are used, then device structure is simple, but electrostatic capacitance between drain and gate electrodes is high

Engineering Contradiction:

Improveelectrostatic capacitanceVSAvoidimpurity region configuration

Core Design Contradiction:

Loss of energyVSDevice complexity

Solution Approach 1:

The impurity region is divided into multiple distinct regions (first impurity region, second impurity region, third impurity region, and fourth impurity region) with alternating conductivity types. This segmentation allows each region to serve specific functions in controlling electric field distribution, thereby reducing electrostatic capacitance between drain and gate electrodes while maintaining manageable device complexity through systematic structuring.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different impurity regions are assigned different conductivity types (first conductivity type or second conductivity type) and positioned at specific locations between the drain electrode and gate pad. This local differentiation of electrical properties enables precise control of electric field lines in different areas, effectively reducing parasitic capacitance where it occurs most while maintaining overall device performance.

Inventive Principle:

Principle #3Local quality

2Reliability

If impurity regions with alternating conductivity types are introduced, then electrostatic capacitance is reduced, but manufacturing complexity increases

Engineering Contradiction:

Improveswitching characteristicsVSAvoidimpurity region formation

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The method performs preliminary actions by forming insulating films and impurity regions in a predetermined sequence before final electrode formation. The insulating film is formed covering the main surface, then impurity regions are formed through this film in alternating conductivity patterns, establishing the electrical field control structure before drain and gate electrodes are created, thereby simplifying subsequent manufacturing steps.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

An insulating film serves as an intermediary layer during the formation process. The insulating film is formed covering the main surface of the semiconductor substrate, and impurity regions are formed through this insulating film. This intermediary structure allows precise control of impurity region formation, enables alternating conductivity types, and simplifies the overall manufacturing process by providing a controlled medium for subsequent processing steps.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The configuration reduces electrostatic capacitance and enhances switching characteristics by blocking electric field lines and reducing parasitic capacitance, leading to improved performance in silicon carbide semiconductor devices.

Implementation Method 1

Both the second impurity region and the fourth impurity region can block lines of electric force generated from the drain electrode toward the gate pad

Methodology Applied

Scientific EffectElectric field blocking: Electric Field

Implementation Method 2

Each of the first impurity region, the second impurity region, the third impurity region, and the fourth impurity region is located between the gate pad and the drain electrode

Methodology Applied

Scientific EffectParasitic capacitance reduction: Parasitic Capacitance

Data Source

PatentUS11233127B2Silicon carbide semiconductor device

Publication Date: 2022.01.25 MITSUMI ELECTRIC CO LTD

AI summary

A silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. A gate pad faces the first main surface. A drain electrode is in contact with the second main surface. The silicon carbide substrate includes a first impurity region constituting the second main surface and having a first conductivity type, a second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type, a third impurity region provided on the second impurity region and having the first conductivity type, and a fourth impurity region provided on the third impurity region, constituting the first main surface, and having the second conductivity type. Each of the first impurity region, the second impurity region, the third impurity region, and the fourth impurity region is located between the gate pad and the drain electrode.