SiC Field Effect Transistor Drift Layer Segmentation for ON-Resistance Reduction
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Solution Overview
Problem
The challenge in silicon carbide field effect transistors is to reduce ON-resistance while maintaining high breakdown voltage, as miniaturization increases JFET resistance, making it difficult to determine impurity concentration distribution in field relieving regions without affecting adjacent layers.
Innovation Solution
A semiconductor device structure with a first and second drift layer of varying impurity concentrations, where the field relieving region is formed in the first drift layer adjacent to the first well region, allowing for independent impurity concentration determination and reduced resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the impurity concentration of the drift layer is increased to reduce ON-resistance, then the ON-resistance decreases, but the impurity concentration distribution of the field relieving region becomes difficult to determine
Solution Approach 1:
The drift layer is divided into two separate layers: a first drift layer with lower impurity concentration and a second drift layer with higher impurity concentration. This segmentation allows the field relieving region to be formed in the first drift layer with precise impurity control, while the second drift layer provides the necessary high impurity concentration for low ON-resistance without interfering with the field relieving region's impurity distribution.
Solution Approach 2:
Different regions of the device are given different impurity concentrations tailored to their specific functions. The first drift layer region containing the field relieving region has lower impurity concentration for precise control, while the second drift layer has higher impurity concentration for reducing overall ON-resistance. This local differentiation resolves the contradiction between global resistance reduction and local precision control.
2Productivity
If miniaturization is implemented to improve device performance, then device size decreases, but the JFET region resistance sharply increases raising ON-resistance
Solution Approach 1:
The invention changes the impurity concentration parameter by introducing a second drift layer with higher impurity concentration than the first drift layer. This parameter change compensates for the increased resistance caused by miniaturization, allowing the device to achieve both small size and low ON-resistance by optimizing the impurity concentration distribution in the drift layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces ON-resistance in the field relieving region while maintaining control over impurity concentration distribution, enhancing the performance of silicon carbide field effect transistors.
Implementation Method 1
The first drift layer is formed of silicon carbide including a first conductivity type impurity of first concentration, and the second drift layer is formed of silicon carbide including a first conductivity type impurity of second concentration higher than the first concentration
Data Source
AI summary
A semiconductor device and a method of manufacturing the same, to appropriately determine an impurity concentration distribution of a field relieving region and reduce an ON-resistance. The semiconductor device includes a substrate, a first drift layer, a second drift layer, a first well region, a second well region, a current control region, and a field relieving region. The first well region is disposed continuously from an end portion adjacent to the vicinity of outer peripheral portion of the second drift layer to a portion of the first drift layer below the vicinity of outer peripheral portion. The field relieving region is so disposed in the first drift layer as to be adjacent to the first well region.