SiC Drift Region Layout for Lower Ron-Qoss Switching Loss
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Solution Overview
Problem
Existing silicon carbide semiconductor devices face challenges in reducing the product of on-resistance (Ron) and output charge amount (Qoss), which affects their performance, particularly in achieving low loss and high temperature operation.
Innovation Solution
The semiconductor device incorporates a silicon carbide layer with specific impurity concentration regions, including high-concentration and low-concentration regions alternately provided below the body regions, which reduces on-resistance and output charge amount by optimizing the impurity distribution and structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional silicon carbide structures are used, then device simplicity is maintained, but the product of on-resistance and output charge amount cannot be reduced
Solution Approach 1:
The drift region is segmented into multiple alternating high-concentration and low-concentration impurity regions. This segmentation creates a multi-layered structure where each layer serves a specific function: high-concentration regions promote on-current spreading to reduce on-resistance, while low-concentration regions extend the depletion layer to reduce output charge amount. The segmented structure resolves the contradiction by distributing different functional responsibilities across distinct regions.
Solution Approach 2:
Different impurity concentration regions are created within the drift region to provide local quality variations. The high-concentration regions locally enhance current spreading capability, while low-concentration regions locally extend depletion layer width. This local quality differentiation allows simultaneous optimization of both on-resistance and output charge amount without requiring complex device-level modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the product of on-resistance and output charge amount, enhancing the performance of silicon carbide semiconductor devices by promoting on-current spreading and extending the depletion layer, thereby improving operational efficiency and stability.
Implementation Method 1
extending the depletion layer
Implementation Method 2
promoting on-current spreading
Data Source
AI summary
A semiconductor device according to an embodiment includes a silicon carbide layer having a first face and a second face; a first silicon carbide region of a first conductivity type; a second silicon carbide region of a second conductivity type; a third silicon carbide region of the first conductivity type in the silicon carbide layer in this order in a direction from the second face to the first face; and a gate electrode. The first silicon carbide region includes a first region, second regions, and third regions. The second regions and the third regions are provided between the first region and the second silicon carbide region. The second regions and the third regions are alternately provided in a first direction parallel to the first face, and the first conductivity type impurity concentration of the second regions is higher than those of the first region and the third regions.