Silicon Carbide Dual-Mesa SIT Gate Junction Fabrication
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Solution Overview
Problem
Conventional silicon carbide (SiC) Static Induction Transistors (SITs) are limited to high frequency ranges due to power gain roll-off above 500 MHz, and manufacturing difficulties and reliability issues hinder their use in higher voltage and temperature applications, especially in L-Band RF systems, where they are outperformed by silicon devices.
Innovation Solution
The fabrication of a vertical-sidewall dual-mesa SiC SIT with angled ion implantation to form a gate junction, reducing parasitic gate capacitance and allowing for higher frequency performance, improved manufacturability, and increased voltage handling capabilities by creating a more robust and efficient transistor structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If Schottky barrier gate control is used with vertical sidewall contacts, then device structure is achieved, but manufacturing complexity increases and reliability decreases
Solution Approach 1:
The patent introduces an intermediary p-type gate region that mediates between the n-type source/drain regions and the channel. This gate region is formed by ion implantation through a patterned oxide mask, serving as an intermediate step that simplifies the overall fabrication process while achieving the desired device structure with vertical sidewall contacts.
Solution Approach 2:
The patent replaces the mechanical/physical process of forming Schottky barrier contacts on vertical sidewalls with a chemical/diffusion-based ion implantation process. Instead of requiring precise angled metal evaporation and lift-off to create Schottky contacts, the invention uses ion implantation through planar oxide masks to form the gate region, substituting a simpler, more reliable fabrication approach.
2Device complexity
If Schottky barrier gate control is used, then device structure is achieved, but reliability decreases due to poor breakdown and reverse leakage characteristics
Solution Approach 1:
The patent changes the fundamental parameter of gate formation from Schottky barrier contact to ion-implanted p-type region. This parameter change transforms the gate's electrical characteristics, achieving superior breakdown voltage and reverse leakage performance while maintaining the vertical sidewall contact structure. The ion implantation energy and dose are optimized to achieve the desired junction depth and doping concentration.
3Ease of manufacture
If conventional single-mesa structure is used, then manufacturing is simplified, but parasitic gate capacitance increases reducing frequency performance
Solution Approach 1:
The patent segments the device structure into distinct source and drain mesas with vertical sidewalls, separated by the gate region. This segmentation allows for optimized geometry that reduces the overlap area between gate and channel, thereby reducing parasitic gate capacitance. The dual-mesa structure with vertical sidewalls enables better control of the electric field distribution and reduces capacitive coupling.
4Stress or pressure
If conventional SiC SIT devices are used, then high voltage operation is achieved, but frequency range is limited above 500 MHz due to power gain roll-off
Solution Approach 1:
The patent changes key geometric parameters of the device structure, including the channel length, gate width, and mesa dimensions, to optimize frequency performance while maintaining high voltage capability. The vertical sidewall geometry and reduced parasitic capacitance enable the device to operate at L-Band frequencies (1-1.5 GHz) while preserving the high breakdown voltage characteristics of SiC material.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual-mesa SiC SIT achieves higher frequency performance, increased power density, and improved reliability by minimizing parasitic capacitance and optimizing transconductance, enabling operation in L-Band RF systems with higher voltages and temperatures, surpassing the limitations of conventional SiC and silicon devices.
Implementation Method 1
The junction gate is formed by implanting acceptor impurities, typically aluminum (Al), into the gate region using the channel mesa, with oxide sidewall spacers as the implant mask.
Data Source
AI summary
A vertical-sidewall dual-mesa static induction transistor (SIT) structure includes a silicon carbide substrate having a layer arrangement formed thereon. Laterally spaced ion implanted gate regions are defined in the layer arrangement. Source regions are defined in the layer arrangement. Each of the source regions can include a channel mesa having a source mesa disposed thereon. The source mesa includes upright sidewalls relative to a principal plane of the substrate defining a horizontal dimension thereof. The channel mesa includes upright sidewalls relative to the source mesa and the principal plane of the substrate. Also disclosed is a method of fabricating a vertical-sidewall dual-mesa SiC transistor device. The method includes implanting ions at an angle relative to a principal plane of the substrate to form gate junctions in upper portions of the substrate and lateral portions of the upright channel mesas.