SiC Semiconductor Layout for Hole Current Extraction at Edge Termination

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional silicon carbide semiconductor devices face challenges in reducing ON resistance while maintaining breakdown voltage, leading to increased displacement current and potential destruction at the active region due to concentrated hole current.

Innovation Solution

The semiconductor device incorporates a source ring region surrounding the gate ring region, featuring a second source electrode with a wider contact area and a plating film to reduce resistance, thereby extracting hole current from the edge termination region and mitigating current concentration at the active region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If the edge termination region is designed to sustain breakdown voltage, then breakdown voltage is improved, but hole current concentrates at the active region causing potential destruction

Engineering Contradiction:
Improvebreakdown voltageVSAvoidhole current concentration
Core Design Contradiction:
StrengthVSObject-affected harmful factors

Solution Approach 1:

The source ring region acts as an intermediary structure between the gate ring region and the edge termination region. It provides a dedicated path for hole current extraction through the second source electrode, preventing hole current from concentrating at the active region while maintaining the edge termination region's breakdown voltage sustaining capability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The device structure is segmented into distinct functional regions: the active region for main current flow, the gate ring region for gate control, the source ring region for hole current extraction, and the edge termination region for breakdown voltage sustenance. This segmentation allows each region to optimize its specific function without interfering with others

Inventive Principle:
Principle #1Segmentation

2Reliability

If a plating film is added to reduce resistance, then ON resistance is reduced, but device structure becomes more complex

Engineering Contradiction:
ImproveON resistanceVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The plating film is merged with the second source electrode to form a unified low-resistance contact structure. This combination reduces ON resistance by providing an excellent electrical contact interface while avoiding the need for separate complex electrode and plating structures

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively reduces ON resistance, suppresses destruction at the edge termination region, and improves breakdown tolerance by facilitating the extraction of hole current and reducing current concentration at the active region.

Implementation Method 1

a first plating film selectively provided on the first source electrode

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS12230704B2Semiconductor device
Publication Date: 2025.02.18 FUJI ELECTRIC CO LTD
  • US12230704B2 patent drawing
  • US12230704B2 patent drawing
  • US12230704B2 patent drawing

AI summary

A semiconductor device has an active region through which a main current flows, a gate ring region surrounding a periphery of the active region, a source ring region surrounding a periphery of the gate ring region, and a termination region surrounding a periphery of the source ring region. The semiconductor device has a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, and further, in the active region, first semiconductor regions of the first conductivity type, a gate insulating film, first gate electrodes, an interlayer insulating film, a first first-electrode, a first plating film, and a second electrode. The semiconductor device has, in the source ring region, a second first-electrode provided at a surface of the second semiconductor layer, and a second plating film provided on the second first-electrode.