SiC Semiconductor Edge Termination with Spatial Modulation JTE
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Solution Overview
Problem
Conventional silicon carbide semiconductor devices face reliability issues due to voltage withstanding structure design, where the depth position of p-type regions is shallow, leading to electric field concentration and reduced withstand voltage in the edge termination region, and the insulating layer's negative charge affects the edge termination region's reliability over time.
Innovation Solution
A silicon carbide semiconductor device with a spatial modulation JTE structure where p-type and p−-type regions are positioned deeper than the front surface, forming a concentric pattern to mitigate electric field concentration and stabilize the withstand voltage, and an n-type surface region is added to counteract charge effects on the insulating layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If p-type regions are positioned shallow in the edge termination region, then the manufacturing process is simpler, but electric field concentration occurs and withstand voltage is reduced
Solution Approach 1:
The patent transitions from shallow p-type region positioning to deep p-type region positioning extending toward the back surface of the semiconductor substrate. This depth dimension change allows the p-type regions to effectively distribute and mitigate electric field concentration, thereby enhancing the withstand voltage of the edge termination region while maintaining manufacturing feasibility through extended ion implantation or epitaxial growth processes.
2Reliability
If p-type regions are positioned deeper in the semiconductor substrate, then electric field concentration is mitigated and withstand voltage is enhanced, but the manufacturing complexity increases
Solution Approach 1:
The patent implements spatial modulation of the p-type region configuration by alternating between higher-concentration and lower-concentration p-type regions at different depths and positions. This local quality variation allows precise control of electric field distribution in the edge termination region, achieving enhanced withstand voltage while managing manufacturing complexity through targeted impurity concentration modulation rather than uniform deep positioning throughout.
3Reliability
If conventional JTE structure is used, then the edge termination region can be formed, but electric field distribution is insufficient and withstand voltage is not stable
Solution Approach 1:
The patent divides the edge termination region into multiple segments with alternating p-type and p−-type regions arranged in a spatial modulation pattern. This segmentation creates a stepped impurity concentration distribution that progressively modulates the electric field from the active region toward the edge termination region, achieving stable withstand voltage characteristics while the segmented structure manages complexity through systematic alternating patterns rather than monolithic design.
4Ease of manufacture
If the insulating layer is used for gate isolation, then device isolation is achieved, but negative charge accumulation in the insulating layer degrades edge termination region reliability over time
Solution Approach 1:
The patent applies preliminary anti-action by positioning deep p-type regions and spatial modulation structures in the edge termination region before operation begins. These pre-configured doped regions create a robust electric field distribution that counteracts and compensates for the detrimental effects of negative charge accumulation in the insulating layer over time, thereby maintaining edge termination region reliability and stable withstand voltage characteristics throughout the device's operational lifetime.
Data Source
AI summary
In an edge termination region, p-type regions and p−-type regions configuring a spatial modulation JTE structure are selectively provided at depth positions apart from a front surface of a semiconductor substrate. Respective bottoms of the p-type regions and the p−-type regions are at depth positions deeper from the front surface of the semiconductor substrate than is a bottom of a p-type peripheral region of a peripheral portion of an active region. An outer-side corner of the bottom of the p-type peripheral region is surrounded by an innermost one of the p-type regions and is free from contact with an n−-type drift region of the edge termination region.