SiC Semiconductor Edge Termination with Space-Modulated Regions
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Solution Overview
Problem
Conventional silicon carbide semiconductor devices face issues with high electric field strength at the surface protecting film, leading to electrical discharge and dielectric breakdown when sealed with a gel, due to the shorter edge length required for maintaining breakdown voltage, which increases the chip size unnecessarily.
Innovation Solution
The silicon carbide semiconductor device incorporates a breakdown voltage structure with longer edge termination regions and space-modulated regions, where the impurity concentrations and lengths of electric field mitigating layers and space-modulated regions are optimized to reduce electric field strength at the surface protecting film, maintaining the edge length and breakdown voltage while suppressing electrical discharge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional JTE structure with shorter edge termination region is used, then chip size is reduced, but electric field strength at surface protecting film increases causing electrical discharge and dielectric breakdown
Solution Approach 1:
The patent applies local quality by creating space-modulated regions with varying impurity concentrations (first sub-region with higher concentration, second sub-region with lower concentration) within the edge termination region. This non-uniform impurity distribution locally modifies electric field characteristics at different positions, reducing peak electric field strength at the surface protecting film while maintaining adequate breakdown voltage, thus preventing electrical discharge without increasing chip size.
Solution Approach 2:
The patent changes the impurity concentration parameter within the edge termination region by introducing space-modulated regions with different impurity concentrations (first sub-region having higher impurity concentration than second sub-region). This parameter variation optimizes the electric field distribution, reducing electric field strength at the surface protecting film interface and preventing dielectric breakdown while maintaining compact chip dimensions.
2Reliability
If edge termination region length is increased to reduce electric field strength, then electrical discharge is suppressed, but chip size increases
Solution Approach 1:
Instead of uniformly increasing the edge termination region length, the patent applies local quality by creating space-modulated regions with varying impurity concentrations within a compact edge termination structure. The first sub-region with higher impurity concentration and the second sub-region with lower impurity concentration are arranged alternately, providing localized electric field control that suppresses electrical discharge without requiring an extended edge termination region, thus avoiding chip size increase.
Solution Approach 2:
The patent segments the edge termination region into multiple space-modulated regions with different impurity concentration profiles (first sub-region and second sub-region alternating). This segmentation allows different portions of the edge termination region to perform specialized functions: the higher concentration first sub-region provides strong field control near the active region, while the lower concentration second sub-region manages the field near the surface protecting film, achieving effective electrical discharge suppression in a compact structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces electric field strength at the surface protecting film and interface, preventing electrical discharge and dielectric breakdown, thereby enhancing device reliability and maintaining breakdown voltage similar to conventional structures.
Implementation Method 1
Points of electric field concentration at outer edges of the electric field mitigating regions constituting the JTE structure are distributed, whereby maximum electric field strength is reduced
Data Source
AI summary
In an edge termination region, first to third electric field mitigating layers are provided in a concentric shape surrounding an active region. Between adjacent first to third electric field mitigating layers, p-type first to third space-modulated regions are provided each of which is closer to a chip edge than is the third electric field mitigating layer. Each of the space-modulated regions is formed by, from an inner side, a low-concentration sub-region and a high-concentration sub-region arranged to alternately repeat in a concentric shape surrounding the electric field mitigating layer on the inner side. Preferable, lengths (Lb1, Lb2, Lb3) of the first to third space-modulated regions are set to satisfy Lb1≤Lb2<Lb3 and preferably lengths (La1, La2, La3) of the first to third electric field mitigating layers are set to satisfy La1<La2<La3. A rate of increase of the lengths of the first to third electric field mitigating layers may be constant.