SiC Device Electrode Contact Resistance via Conductive Oxidation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a demand for further reducing contact resistance between a semiconductor base body and an electrode layer in silicon carbide semiconductor devices.
Innovation Solution
Forming an electrode layer over a reaction layer with a predetermined conductive oxidation layer interposed between, rather than directly forming it on the reaction layer, using specific plasma ashing and etching steps with gases like oxygen, hydrogen, and acids such as hydrochloric, nitric, and hydrofluoric acids to optimize the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the electrode layer is formed directly on the reaction layer, then the manufacturing process is simple, but the contact resistance between the semiconductor base body and the electrode layer is high
Solution Approach 1:
A conductive oxidation layer is introduced as an intermediary layer between the reaction layer and the electrode layer. This oxidation layer, formed through plasma ashing and controlled etching, serves as a mediator that reduces contact resistance while maintaining process feasibility. The conductive oxidation layer has properties that facilitate better electrical contact than direct deposition on the reaction layer.
Solution Approach 2:
The surface properties of the reaction layer are changed through plasma ashing and etching processes, which modify the chemical and physical state of the surface. By controlling the thickness and conductivity of the oxidation layer through parameter adjustment (plasma power, etching time, gas composition), optimal contact resistance is achieved.
2Reliability
If the conductive oxidation layer is made thicker, then the contact resistance is reduced, but the adhesiveness between the electrode layer and reaction layer deteriorates
Solution Approach 1:
The thickness of the conductive oxidation layer is precisely controlled within a specific range (0.3nm to 2.25nm) to achieve optimal balance between contact resistance and adhesiveness. This parameter optimization ensures that the oxidation layer is thick enough to provide conductive pathways but thin enough to maintain strong bonding between the electrode layer and reaction layer.
Solution Approach 2:
The oxidation layer exhibits different functional properties at different thicknesses: at the optimal thickness range, it provides sufficient conductivity while maintaining adequate mechanical adhesion. The local quality of the interface is optimized to simultaneously satisfy electrical and mechanical requirements.
3Manufacturing precision
If the CMP process is used to form the reaction layer, then the surface flatness is improved, but the manufacturing cost and time increase
Solution Approach 1:
The mechanical CMP (chemical mechanical polishing) process is replaced with a combination of plasma ashing and chemical etching processes. This substitution eliminates the need for mechanical polishing while achieving the desired surface flatness and reaction layer formation, thereby reducing manufacturing cost and processing time.
Solution Approach 2:
The patent employs consumable chemicals (acids such as hydrofluoric acid, nitric acid, and hydrochloric acid) and plasma gases that can be easily replenished and disposed of, replacing the expensive and time-consuming CMP process. These chemical processes provide a more economical and efficient alternative for surface preparation and reaction layer formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces contact resistance between the semiconductor base body and the electrode layer, improves device reliability by preventing delamination, and enhances productivity by replacing the costly CMP process with etching.
Implementation Method 1
a heat treatment step where the silicon carbide layer 910 and the conductive layer 922 are made to react with each other thus forming an alloy layer formed of a reaction layer 920 which is in contact with the silicon carbide layer 910
Implementation Method 2
by forming an electrode layer over a reaction layer with a predetermined conductive oxidation layer interposed therebetween instead of directly forming the electrode layer on the reaction layer
Implementation Method 3
an etching step where at least a portion of the silicide layer 924 is removed using an acid thus exposing at least a portion of a surface of the reaction layer 920
Data Source
Figure 1
Figure 2A~2E
Figure 3A~3E
AI summary
A silicon carbide semiconductor device 100 of the present invention includes: a silicon carbide layer 110; a reaction layer 120 which is in contact with the silicon carbide layer 110; a conductive oxidation layer 130 which is in contact with the reaction layer 120; and an electrode layer 140 which is formed over the reaction layer 120 with the conductive oxidation layer 130 interposed therebetween. It is preferable that a thickness of the conductive oxidation layer 130 falls within a range of 0.3nm to 2.25nm. According to the silicon carbide semiconductor device 100 of the present invention, by forming the electrode layer 140 over the reaction layer 120 with the conductive oxidation layer 130 interposed therebetween instead of directly forming the electrode layer 140 on the reaction layer 120, contact resistance between the semiconductor base body and the electrode layer can be further reduced. According to the silicon carbide semiconductor device 100 of the present invention, the thickness of the conductive oxidation layer 130 falls within a range of 0.3nm to 2.25nm and hence, the contact resistance between the semiconductor base body and the electrode layer can be still further reduced.