SiC Epitaxial Wafer Defect Conversion via High-Rate Growth
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Solution Overview
Problem
Current methods for producing SiC epitaxial wafers with larger sizes, such as 6 inches or more, face challenges in achieving low basal plane dislocation and intrinsic 3C triangular defect densities, which are critical for reducing device killer defects and improving device yield and quality.
Innovation Solution
A method involving a ramping step to gradually adjust crystal growth conditions to high-rate epitaxial growth conditions, including a high-rate growth step with a growth rate of 50 μm/h or more, and a buffer layer with a higher carrier concentration than the drift layer, to convert basal plane dislocations into threading edge dislocations efficiently, thereby reducing defect densities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of SiC epitaxial wafer is increased to 6 inches or more, then productivity and device yield are improved, but basal plane dislocation density and intrinsic 3C triangular defect density increase
Solution Approach 1:
The epitaxial growth process is divided into multiple stages: initial growth stage, intermediate growth stage, and final growth stage. Each stage has optimized growth rates and conditions to progressively manage defect formation while maintaining high productivity for large 6-inch wafers
Solution Approach 2:
Growth rate parameters are dynamically adjusted throughout the epitaxial process. The growth rate is increased from initial low rates to final high rates (50-200 μm/h), allowing control over defect formation while achieving high productivity for large wafers
2Manufacturing precision
If thermal stress is applied to reduce basal plane dislocation density, then manufacturing precision is improved, but process complexity and energy consumption increase
Solution Approach 1:
Temperature parameters are optimized within a specific range (1600-2000°C) to naturally promote conversion of basal plane dislocations to threading edge dislocations without requiring additional thermal stress processing steps
Solution Approach 2:
The process leverages the natural tendency of basal plane dislocations to convert to threading edge dislocations under controlled epitaxial conditions, transforming a potentially harmful defect into a less harmful one through optimized growth parameters rather than additional processing
3Manufacturing precision
If C/Si ratio is increased to reduce basal plane dislocation density, then manufacturing precision is improved, but material cost and process complexity increase
Solution Approach 1:
The C/Si ratio is optimized within a specific range (0.5-2.0) to achieve effective conversion of basal plane dislocations while avoiding excessive carbon incorporation that would increase material costs and cause other defects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in SiC epitaxial wafers with basal plane dislocation and intrinsic 3C triangular defect densities of 0.1 pieces/cm2 or less, enhancing device operation, yield, and quality, particularly for larger wafer sizes.
Implementation Method 1
Most of the basal plane dislocations in the SiC single crystal substrate may be converted into threading edge dislocations (TED) during formation of the epitaxial layer
Implementation Method 2
The SiC epitaxial wafer can be obtained by forming (growing) an epitaxial layer (film), which becomes an active region of the device, on a SiC single crystal substrate by using a chemical vapor deposition (CVD) method
Data Source
AI summary
This SiC epitaxial wafer includes: a SiC single crystal substrate of which a main surface has an off-angle of 0.4° to 5° with respect to (0001) plane; and an epitaxial layer provided on the SiC single crystal substrate, wherein the epitaxial layer has a basal plane dislocation density of 0.1 pieces/cm2 or less that is a density of basal plane dislocations extending from the SiC single crystal substrate to an outer surface and an intrinsic 3C triangular defect density of 0.1 pieces/cm2 or less.