Silicon Carbide Epitaxial Wafer Growth for Defect Suppression
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Solution Overview
Problem
Silicon carbide epitaxial wafers suffer from defects such as dislocations and crystal defects, leading to discrepancies in semiconductor devices.
Innovation Solution
A method involving the formation of a first silicon carbide layer at a controlled growth rate of 0.5-2 μm/h with a thickness of 1-100 nm, followed by a second layer at a higher growth rate of 2-100 μm/h, reducing bump density and effectively burying defects, thereby minimizing stacking faults and other defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a silicon carbide epitaxial wafer is made by epitaxially growing a SiC layer with a prescribed concentration of impurities on a SiC wafer, then semiconductor devices can be manufactured, but many defects occur in the silicon carbide epitaxial wafer causing discrepancies in the semiconductor devices
Solution Approach 1:
The epitaxial growth process is divided into multiple stages with different growth rates. The patent employs a two-stage growth method where the first stage grows at a slower rate (0.1-1.0 μm/h) to form a initial layer, and the second stage grows at a faster rate (1.0-10.0 μm/h) to complete the layer. This segmentation allows defect suppression during the critical initial growth phase while maintaining overall manufacturing efficiency.
2Productivity
If the growth rate is increased to improve productivity, then manufacturing efficiency increases, but defect formation increases leading to more discrepancies
Solution Approach 1:
The patent applies preliminary action by conducting the slow growth stage first to establish a defect-free foundation layer before transitioning to fast growth. This preliminary slow growth phase allows impurities to be incorporated in a controlled manner and prevents dislocation propagation, creating a clean substrate for subsequent high-rate growth that maintains both speed and quality.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting the growth rate parameter during the epitaxial process. The growth rate is changed from a first value (0.1-1.0 μm/h) to a second value (1.0-10.0 μm/h) at a predetermined timing, allowing optimization of both defect suppression and productivity by exploiting the different roles of slow and fast growth at different stages.
3Reliability
If impurities are incorporated to achieve desired electrical properties, then device functionality is achieved, but defect density increases
Solution Approach 1:
The patent applies local quality by creating different impurity concentration profiles in different regions and stages of the epitaxial layer. The slow growth stage incorporates impurities at a controlled rate to achieve desired electrical properties, while the fast growth stage maintains a different impurity profile. This spatial and temporal variation in impurity incorporation allows optimization of electrical performance in specific regions while minimizing overall defect density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces defects in silicon carbide epitaxial wafers, suppressing stacking faults and enhancing the reliability and productivity of semiconductor devices.
Implementation Method 1
forming a first silicon carbide layer on a silicon carbide wafer by epitaxially growing silicon carbide at a first growth rate
Data Source
AI summary
A method for manufacturing a silicon carbide epitaxial wafer includes forming a first silicon carbide layer on a silicon carbide wafer by epitaxially growing silicon carbide at a first growth rate of not less than 0.5 μm/h and not more than 2 μm/h to have a film thickness of not less than 1 nm and not more than 100 nm, a bump density of the first silicon carbide layer being a first density; and forming a second silicon carbide layer on the first silicon carbide layer by epitaxially growing silicon carbide at a second growth rate of greater than 2 μm/h and not more than 100 μm/h to have a film thickness of not less than 4 μm and not more than 100 μm, a bump density of the second silicon carbide layer being a second density that is less than the first density.