SiC Epitaxial Wafer Triangular Defect Reduction
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Solution Overview
Problem
The yield of SiC epitaxial wafers is reduced due to triangular defects, which are caused by minute SiC grains adhering to the substrate during epitaxial growth, and unique defects that occur under general growth conditions, especially in high breakdown voltage devices with film thicknesses of several tens of μm or more.
Innovation Solution
A SiC epitaxial wafer with a film thickness of 18 μm or more and 350 μm or less, having an arithmetic average roughness of 0.60 nm or more and 3.00 nm or less, and an impurity concentration of 1×10^14/cm^3 or more and 5×10^15/cm^3 or less, is formed using a CVD method with specific pressure, C/Si ratio, and growth temperature conditions to reduce triangular defects and improve crystal uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the film thickness of the epitaxial layer is increased to achieve high breakdown voltage (several tens of μm or more), then the breakdown voltage performance is improved, but triangular defects become more noticeable and device yield decreases
Solution Approach 1:
The patent applies parameter changes by precisely controlling epitaxial growth conditions including temperature (1400-1750°C), pressure (760-100 Pa), C/Si ratio (0.5-2.0), and V/III ratio (5-50) to form high-quality thick epitaxial layers with reduced triangular defects, enabling both high breakdown voltage and high device yield
2Productivity
If general epitaxial growth conditions are used, then the growth process is simple and fast, but unique triangular defects occur that reduce crystal uniformity
Solution Approach 1:
The patent changes growth parameters including using specific temperature ranges (1400-1750°C), pressure conditions (760-100 Pa), and ratios (C/Si: 0.5-2.0, V/III: 5-50) to achieve both high growth speed and high crystal uniformity, eliminating the need to choose between productivity and precision
3Strength
If the epitaxial layer is grown thicker to meet high breakdown voltage specifications, then the device performance is improved, but the impact of triangular defects is amplified
Solution Approach 1:
The patent uses parameter changes during epitaxial growth (temperature 1400-1750°C, pressure 760-100 Pa, C/Si ratio 0.5-2.0, V/III ratio 5-50) to control defect formation mechanisms, enabling thick layers to be grown with minimized triangular defects that would otherwise be amplified at greater thicknesses
Solution Approach 2:
The patent converts the potential harm of thick epitaxial layers (which amplify defects) into a benefit by using controlled growth parameters that suppress triangular defect formation, allowing the thick layer to provide high breakdown voltage without the usual defect penalty
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach significantly reduces the number of triangular defects, enhancing the device yield by ensuring uniform surface roughness and impurity concentration, thereby improving the reliability and performance of SiC power devices.
Implementation Method 1
a drift layer of a semiconductor device needs to be formed on a SiC substrate in advance. The drift layer is elaborately formed by controlling the film thickness and the carrier concentration in the crystal precisely by a chemical vapor deposition (CVD) method or the like.
Data Source
AI summary
The object of the present invention is to enhance the device yield of SiC epitaxial wafers. The SiC epitaxial wafer includes a drift layer which is a SiC epitaxial layer. The drift layer has a film thickness of 18 μm or more and 350 μm or less and has arithmetic average roughness of 0.60 nm or more and 3.00 nm or less, and the impurity concentration thereof is 1×1014/cm3 or more and 5×1015/cm3 or less.