SiC Vertical FET Avalanche Generating Unit
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Solution Overview
Problem
Conventional silicon carbide vertical field effect transistors face breakdown issues in the gate insulating film when high voltage is applied to the drain electrode, leading to reduced reliability due to a large electric field.
Innovation Solution
Incorporating a high-concentration second-conductive-type region or a shallow second-conductive-type region under the second-conductive-type region, which generates an avalanche when high voltage is applied to the drain electrode, thereby avoiding a large electric field on the gate insulating film.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high voltage is applied to the drain electrode, then the switching capability of the MOSFET is improved, but a large electric field is applied to the gate insulating film causing insulation breakdown or reduced reliability
Solution Approach 1:
An N-type drift layer is introduced as an intermediary between the P-type base region and the N-type source region. This drift layer acts as a mediator that distributes and reduces the electric field concentration at the gate insulating film interface, allowing high voltage to be handled without causing insulation breakdown. The drift layer effectively decouples the high voltage stress from the gate insulating film while maintaining the switching capability.
Solution Approach 2:
The patent modifies the electrical parameters of the semiconductor structure by creating a carefully controlled P-type base region with specific doping concentration and depth, followed by an N-type drift layer with optimized doping levels. By changing these parameters - particularly the doping concentration gradient and layer thicknesses - the electric field distribution is transformed to protect the gate insulating film while preserving high voltage handling capability.
2Ease of manufacture
If a conventional MOSFET structure is used, then the device is simple to manufacture, but breakdown resistance of the gate insulating film is poor under high voltage conditions
Solution Approach 1:
The semiconductor structure is segmented into distinct functional layers: a P-type base region, an N-type drift layer, and an N-type source region. This segmentation allows each layer to be optimized for its specific function - the base region for threshold control, the drift layer for electric field management, and the source region for carrier injection. The segmented structure maintains manufacturing simplicity while significantly improving breakdown resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the breakdown resistance and reliability of the gate insulating film by preventing a large electric field from being applied during high voltage conditions.
Implementation Method 1
an avalanche generating unit is disposed between the first-conductive-type silicon carbide layer and each of the second-conductive-type regions
Data Source
AI summary
A silicon carbide vertical field effect transistor includes a first-conductive-type silicon carbide substrate; a low-concentration first-conductive-type silicon carbide layer formed on a surface of the first-conductive-type silicon carbide substrate; second-conductive-type regions selectively formed on a surface of the first-conductive-type silicon carbide layer; first-conductive-type source regions formed in the second-conductive-type regions; a high-concentration second-conductive-type region formed between the first-conductive-type source regions in the second-conductive-type region; a source electrode electrically connected to the high-concentration second-conductive-type region and a first-conductive-type source region; a gate insulating film formed from the first-conductive-type source regions formed in adjacent second-conductive-type regions, onto the second-conductive-type regions and the first-conductive-type silicon carbide layer; a gate electrode formed on the gate insulating film; and a drain electrode on the back side of the first-conductive-type silicon carbide substrate, wherein an avalanche generating unit is disposed between the second-conductive-type region and the first-conductive-type silicon carbide layer.