SiC FET Gate Finger Coupling for Yield and Parasitic Capacitance
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Solution Overview
Problem
Field-effect transistors with multiple gate fingers suffer from high probability of uncoupling, especially on single-crystal SiC substrates, leading to reduced yield and compromised high-frequency characteristics due to increased parasitic capacitance.
Innovation Solution
The design includes a semiconductor substrate with drain and source ohmic contacts, a drain coupling portion, a gate finger, and a gate power supply line, along with a gate edge coupling portion that couples adjacent gate fingers without intersecting the drain, ensuring stable gate voltage application and reduced parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of gate fingers is increased to achieve high output, then the transistor output capability is improved, but the probability of gate finger uncoupling is increased and yield is dramatically reduced
Solution Approach 1:
The patent merges multiple gate fingers into a unified gate structure where the gate electrodes are continuously connected across the semiconductor substrate. This continuous gate structure eliminates the uncoupling risk between individual gate fingers while maintaining the high output capability achieved through multiple gate elements, thereby resolving the contradiction between power output and manufacturing yield.
2Device complexity
If a gate power supply line intersects with the drain to couple gate fingers, then the gate voltage application is simplified, but the parasitic capacitance between gate and drain is increased and high-frequency characteristics deteriorate
Solution Approach 1:
The patent transitions from a planar two-dimensional layout where gate power supply lines must intersect with drains to a three-dimensional configuration where the continuous gate structure extends across the substrate surface without intersections. The gate electrodes are arranged to follow the contour of the active areas, allowing voltage application without crossing drain regions, thus eliminating parasitic capacitance while maintaining structural simplicity.
3Reliability
If gate fingers are arranged on single-crystal SiC substrate to achieve high performance, then the transistor performance is improved, but the probability of gate finger uncoupling at micro pipe positions is high
Solution Approach 1:
The patent segments the gate structure into multiple gate electrodes that are continuously connected, rather than using discrete gate fingers. This segmented yet continuous design allows the gate structure to navigate around micro pipe positions in the SiC substrate without creating weak coupling points, maintaining both high performance and manufacturing precision by eliminating uncoupling risks at crystal defect locations.
Data Source
AI summary
At least two drain ohmic contacts are arranged to intersect with an active area. A source ohmic contact is arranged between the drain ohmic contacts. A drain coupling portion on an element separating area couples ends of the drain ohmic contacts on the same side thereof. A gate power supply wiring on the element separating area couples gate fingers at the end thereof on the opposite side of the arrangement side of the drain coupling portion. A gate edge coupling portion couples two gate fingers adjacent to each other, sandwiching the source ohmic contact at the end thereof on the arrangement side of the drain coupling portion. The gate edge coupling portion does not intersect with the drain ohmic contact and the drain coupling portion.