Vertical-Channel SiC Power FET Gate Depth Control
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Solution Overview
Problem
In SiC-based junction FETs, achieving a high aspect ratio channel region while controlling gate depth and distance with precision is challenging due to the need for high-energy ion implantation, which increases junction current and requires complex trench formation processes.
Innovation Solution
A vertical-channel type SiC power FET with a floating gate region below the source region and between gate regions, formed by ion implantation, allowing for precise control of channel dimensions and eliminating the need for trench formation, thereby reducing junction current and energy requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If high-energy ion implantation is used to form gate regions, then gate depth can be achieved, but junction current increases and manufacturing complexity increases
Solution Approach 1:
The gate formation process is segmented into two distinct stages: first forming a shallow gate region at low energy to define the gate position and prevent excessive junction current, then forming a deep gate region at high energy to achieve the required gate depth. This segmentation allows each stage to optimize for its specific function without the drawbacks of using high energy throughout the entire process.
Solution Approach 2:
The shallow gate region is formed as a preliminary structure before the deep gate region. This preliminary gate region serves as a template that defines the gate position and limits junction current during subsequent processing steps, including the high-energy ion implantation that forms the deep gate region.
2Length of stationary object
If trench formation is used to form gate regions, then gate depth can be controlled, but device complexity and manufacturing steps increase
Solution Approach 1:
The invention extracts and eliminates the trench formation step from the gate formation process. Instead of forming a physical trench structure and then filling it, the gate regions are formed directly through sequential ion implantation into the drift region, simplifying the manufacturing process while maintaining precise control over gate depth.
Solution Approach 2:
The mechanical trench formation process is replaced with a field-based ion implantation process. Instead of physically etching and filling trenches, the gate regions are created by controlled ion implantation, which allows for more precise depth control and eliminates the complexity of trench formation and filling steps.
3Length of stationary object
If high-energy ion implantation is used for termination structure, then termination depth is achieved, but energy consumption increases
Solution Approach 1:
The shallow gate region is formed as a preliminary structure that defines the gate position and limits junction current during subsequent processing steps, including the high-energy ion implantation that forms the deep gate region.
4Manufacturing precision
If photolithography with high precision is used to control gate distance, then distance control is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The mechanical trench formation process is replaced with a field-based ion implantation process. Instead of physically etching and filling trenches, the gate regions are created by controlled ion implantation, which allows for more precise depth control and eliminates the complexity of trench formation and filling steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of a high-aspect-ratio channel region with improved control over gate depth and distance, reducing junction current and simplifying the manufacturing process, while maintaining high breakdown voltage and switching characteristics.
Implementation Method 1
a gate region is formed by forming a trench in a gate formation region and then conducting ion implantation into the side wall of the trench
Implementation Method 2
ion implantation with markedly high energies (about 2 MeV) is necessary for the formation of a termination structure
Data Source
AI summary
In order to secure the performance of a SiC-based JFET having an impurity diffusion rate lower than silicon-based one, a gate depth is secured while precisely controlling a distance between gate regions, instead of forming gate regions by ion implantation into the side wall of a trench. This means that a channel region defined by a gate distance and a gate depth should have a high aspect ratio. Further, due to limitations of process, a gate region is formed within a source region. Formation of a highly doped PN junction between source and gate regions causes various problems such as inevitable increase in junction current. In addition, a markedly high energy ion implantation becomes necessary for the formation of a termination structure. In the invention, provided is a vertical channel type SiC power JFET having a floating gate region below and separated from a source region and between gate regions.