SiC Device Field Oxide Edge Positioning

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional silicon carbide semiconductor devices experience dielectric breakdown due to electric field concentration at the chip-center-side edge of the poly-silicon layer and edges of the field oxide film, leading to premature destruction under high-temperature and high-voltage conditions.

Innovation Solution

The silicon carbide semiconductor device features a field oxide film with a rectangular ring shape surrounding a first gate poly-silicon layer, where the field oxide film's edges are positioned to avoid direct opposition with the poly-silicon layer, preventing electric field concentration and dielectric breakdown by maintaining a flat surface for the poly-silicon layer and ensuring no step occurs at its surface.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a poly-silicon layer is provided directly beneath the gate metal layer in the edge termination region, then the gate structure can be formed, but electric field concentration occurs at the edges of the poly-silicon layer causing dielectric breakdown

Engineering Contradiction:
Improvegate structure formationVSAvoiddielectric breakdown resistance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

An insulating film is introduced as an intermediary layer between the poly-silicon layer and the gate metal layer in the edge termination region. This mediator prevents direct contact and eliminates the electric field concentration that occurs at the edges of the poly-silicon layer, thereby preventing dielectric breakdown while maintaining the gate structure formation capability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The solution moves from a two-dimensional planar structure to a three-dimensional structure by adding the insulating film layer in the vertical dimension. This dimensional change allows the poly-silicon layer to be positioned beneath the gate metal layer while preventing edge contact through the intermediate insulating layer, resolving the electric field concentration issue

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If the field oxide film extends close to the active region, then better field control is achieved, but electric field concentration occurs at the edges of the field oxide film leading to dielectric breakdown

Engineering Contradiction:
Improvefield controlVSAvoiddielectric breakdown resistance
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The insulating film serves as an intermediary that separates the field oxide film edges from direct opposition with the poly-silicon layer edges. This mediator prevents the formation of high electric field concentration points at the interfaces, allowing the field oxide film to extend close to the active region for better field control without causing dielectric breakdown

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The insulating film is selectively provided only in the edge termination region beneath the gate metal layer, where the electric field concentration problem occurs. This local application maintains field control precision in the active region while preventing dielectric breakdown specifically at the vulnerable edge termination interfaces

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11049964B2Silicon carbide semiconductor device
Publication Date: 2021.06.29 FUJI ELECTRIC CO LTD
  • US11049964B2 patent drawing
  • US11049964B2 patent drawing
  • US11049964B2 patent drawing

AI summary

A first portion of the poly-silicon layer is provided on a first face of a front surface of a semiconductor substrate via a gate insulating film in an edge termination region and configures a gate runner. The first portion opposes an edge p++-type contact region in a depth direction Z. A chip-end-side edge of the first portion is positioned within a plane of the edge p++-type contact region. A field oxide film disposed separated from the poly-silicon layer, extends from a chip end toward a chip center and, on the first face, terminates closer to the chip end than does the first portion. The entire surface of the poly-silicon layer is flat, free of a step due to the field oxide film. A chip-center-side edge of the field oxide film is closer to the chip end than is the edge p++-type contact region and positioned on a p-type base region.