SiC Power MOSFET Fin Structure for Lower Source Resistance
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Solution Overview
Problem
Current silicon carbide (SiC) power MOSFETs face challenges in achieving low on-resistance and high inversion channel mobility, particularly in lower voltage classes, which limits their efficiency and adoption in applications like electric and hybrid electric vehicles due to high on-state and switching losses, as well as interface defect issues affecting channel mobility.
Innovation Solution
The power semiconductor device employs a semiconductor layer stack with pillar-shaped or fin-shaped regions traversing the gate electrode layer, featuring differently doped layers and a gate electrode layer that is laterally overgrown by contact layers, increasing contact area and reducing source resistance, and utilizing a combination of SiC polytypes for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If planar design with p-type implantations is used in n-channel VDMOS, then device structure is simple, but current density is reduced due to parasitic JFET effect
Solution Approach 1:
The patent divides the channel structure into multiple segments by introducing trenches that partition the channel into isolated regions. This segmentation eliminates the parasitic JFET effect by preventing lateral depletion region interaction, thereby maintaining high current density while preserving structural simplicity through standardized trench formation processes.
Solution Approach 2:
The patent introduces an intermediary trench structure filled with insulating material between the p-type implantation regions. This intermediary element acts as a barrier that prevents the formation of parasitic JFET channels while allowing the main current flow to proceed uninterrupted through the n-type drift region.
2Object-generated harmful factors
If trench MOSFET architecture is used to eliminate parasitic JFET, then on-resistance is reduced, but manufacturing complexity increases due to deep trench etching in SiC
Solution Approach 1:
The patent modifies the trench parameters by optimizing trench depth, width, and spacing to achieve effective parasitic JFET elimination without requiring excessively deep trenches. By carefully controlling these geometric parameters, the patent reduces manufacturing complexity while maintaining the electrical performance benefits of trench architecture.
Solution Approach 2:
The patent employs composite structures by filling the etched trenches with insulating materials such as silicon oxide or silicon nitride. This composite approach combines the advantages of SiC for high-power handling with the benefits of insulating materials for electrical isolation, thereby achieving low on-resistance through a manufacturable process that leverages existing semiconductor fabrication capabilities.
3Object-generated harmful factors
If inversion channel mobility is increased through improved gate stacks and SiC/oxide interfaces, then on-resistance is reduced, but interface defect density remains a limiting factor
Solution Approach 1:
The patent converts the potentially harmful interface defects into beneficial nitrogen passivation centers by introducing nitrogen during the oxide formation process. The nitrogen atoms preferentially bond to interface defect sites, transforming high-density interface states that would normally degrade mobility into beneficial passivation that reduces defect density and enhances carrier mobility in the inversion channel.
Solution Approach 2:
The patent optimizes the oxidation parameters and nitrogen introduction conditions to achieve maximum interface passivation effectiveness. By carefully controlling temperature, time, and nitrogen concentration during the gate oxide formation process, the patent maximizes the conversion of interface defects into beneficial nitrogen passivation centers, thereby achieving low on-resistance with improved channel mobility while maintaining interface quality.
Data Source
AI summary
Semiconductor device having first and second main electrodes with gate electrode layer inbetween, semiconductor layer stack between and in electrical contact with the first and second main electrodes having differently doped semiconductor layers. At least two semiconductor layers differ in their conductivity type and/or their doping concentration. Pillar-shaped or fin-shaped regions run through the gate electrode layer, each having a contact layer arranged at the first main electrode with a first doping concentration and a first conductivity type. Each contact layer extends to a side of the gate electrode layer facing the first main electrode, the contact layers of adjacent pillar-shaped or fin-shaped regions merge on the side of the gate electrode layer facing the first main electrode so that the contact layers of adjacent pillar-shaped or fin-shaped regions are arranged continuously on the side of the gate electrode layer facing the first main electrode.