SiC Gate Insulating Film Degradation via Band Offset Engineering
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Solution Overview
Problem
In insulated gate semiconductor devices using silicon carbide, the gate oxide film degrades over time due to high electric fields, leading to reduced credibility and reliability under high voltage conditions.
Innovation Solution
A semiconductor device configuration is introduced, where a second semiconductor layer with a narrower band gap is interposed between the JFET region and the gate insulating film, increasing the band offset and controlling the effective mass of electrons or holes to suppress their injection into the gate insulating film, thereby reducing degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a high electric field is applied to the gate insulating film above the JFET region, then the breakdown voltage property is improved, but the gate insulating film degrades with time
Solution Approach 1:
A P- region with low impurity concentration is introduced as an intermediary layer between the JFET region and the gate insulating film. This intermediary region reduces the electric field strength applied to the gate insulating film while maintaining the high voltage breakdown capability of the device.
Solution Approach 2:
The patent applies local quality by creating a specific region (P- region) with different impurity concentration characteristics than the surrounding areas. The P- region has lower impurity concentration specifically where it interfaces with the gate insulating film, providing localized electric field management without affecting the overall device structure.
2Loss of energy
If the impurity concentration is increased at the ohmic contact portion in heterojunction, then the on-resistance is reduced, but the device complexity increases
Solution Approach 1:
The patent applies local quality by creating a specific region (P- region) with different impurity concentration characteristics than the surrounding areas. The P- region has lower impurity concentration specifically where it interfaces with the gate insulating film, providing localized electric field management without affecting the overall device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses the degradation of the gate insulating film over time, enhancing the reliability and credibility of the semiconductor device under high electric fields by reducing electron or hole injection into the oxide film.
Implementation Method 1
the band offset of the gate insulating film and a semiconductor interface in the JFET region and becomes large, thereby ensuring the control of a current value flowing into the gate insulating film above the JFET region
Data Source
AI summary
Provided is a semiconductor device includes a first semiconductor layer provided on a first main surface of the semiconductor substrate, a plurality of first semiconductor regions selectively provided at upper layer parts of the semiconductor layer, a second semiconductor region selectively provided at an upper layer part of each of the first semiconductor regions, a second semiconductor layer provided on a JFET region corresponding to the first semiconductor layer between the first semiconductor regions, and configured to cover at least a part of the JFET region, a gate insulating film covering the first semiconductor regions and the second semiconductor layer, a third semiconductor layer provided on the second semiconductor layer, a gate electrode provided on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film, a contact hole penetrating through the gate insulating film and the interlayer insulating film, at least the second semiconductor region being exposed to a bottom part thereof, a first main electrode provided on the interlayer insulating film, and configured to electrically connect to the second semiconductor region via the contact hole, and a second main electrode provided on a second main surface of the semiconductor substrate.