SiC Device Gate Oxide Segmentation for Capacitance Reduction
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Solution Overview
Problem
Wide band gap semiconductor devices experience significant switching loss and oscillation phenomena due to high junction capacitance, which restricts their operation frequency and causes energy loss, especially at high switching frequencies.
Innovation Solution
A wide band gap semiconductor device with a high impurity concentration substrate and a low impurity concentration drift layer, featuring selectively arranged channel regions and a gate electrode structure with a gate oxide film, which reduces the drain-source capacitance and drain-gate capacitance, thereby minimizing switching loss and oscillation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a conventional wide band gap semiconductor device structure is used, then high breakdown electric field strength and high thermal conductivity are achieved, but significant switching loss and oscillation phenomena occur due to high junction capacitance
Solution Approach 1:
The device is divided into multiple independent cells, each with its own gate electrode and channel region. The gate electrodes are separated by insulating films, which segment the capacitance into smaller units. This segmentation reduces the total drain-gate capacitance and minimizes oscillation phenomena while maintaining the high breakdown electric field strength and thermal conductivity of the wide band gap semiconductor material.
2Loss of energy
If high impurity concentration is used in the drift layer, then low ON state resistance is achieved, but high junction capacitance increases switching loss and restricts operation frequency
Solution Approach 1:
The insulating films are selectively placed in specific regions between adjacent gate electrodes and channel regions, creating local quality differences. This localized insulation reduces junction capacitance in critical areas without affecting the overall high impurity concentration in the drift layer, thereby maintaining low ON state resistance while reducing switching loss and enabling higher operation frequencies.
3Strength
If high reverse bias voltage is applied to the pn junction, then high withstand voltage is achieved, but the p channel region punches through without the high concentration p base region
Solution Approach 1:
The high concentration p base region is formed in advance beneath each p channel region before the pn junction is subjected to high reverse bias voltage. This preliminary structural preparation ensures that when high voltage is applied, the electric field is properly distributed and the p channel region is supported, preventing punch-through and ensuring reliable high withstand voltage performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces switching loss and prevents oscillation by minimizing the variation of drain voltage feedback to the gate voltage, allowing for higher operational frequencies and reduced energy loss.
Implementation Method 1
reduces the drain-source capacitance and drain-gate capacitance, thereby minimizing switching loss and oscillation
Implementation Method 2
adjacent cells with insulating films between gate electrodes
Data Source
AI summary
A semiconductor device comprises an n+ type SiC semiconductor substrate, an n type low concentration drift layer of an SiC semiconductor on the substrate, p type channel regions selectively arranged in the drift layer with a specified distance between the channel regions, an n type source region selectively arranged in the channel region, a source electrode in common contact with the source region and the channel region, and a gate electrode disposed over the drift layer between two channel regions, and over a part of the channel region positioned between the drift layer and the source region intercalating a gate oxide film therebetween. The drift layer has a low concentration of at most 70% of the concentration that is required to exhibit a specified withstand voltage at a minimum ON resistance.