SiC Gate Formation Using Carbon Capping and ALD Oxide Interface
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The performance of silicon-carbide (SiC) MOSFETs is limited by the high interface state density at the SiC/silicon dioxide (SiO2) interface, leading to low effective channel mobility due to electron trapping and carbon cluster formation, which existing techniques have been unable to effectively address.
Innovation Solution
A method involving the deposition of an amorphous carbon layer as a capping layer and hard mask, followed by high-temperature annealing and selective etching to form a trench structure, and the use of atomic layer deposition (ALD) for a silicon dioxide layer at low temperatures to reduce interface state density, along with interface treatments to prevent carbon clustering and enhance dopant activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SiC/SiO2 interface formation is used, then device structure is simple, but interface state density is high (10^12-10^13 eV^-1 cm^-2) leading to low channel mobility
Solution Approach 1:
An amorphous carbon layer is deposited on the SiC surface before oxide formation to serve as a protective capping layer. This preliminary action prevents carbon contamination and prepares the surface for subsequent processing, ultimately reducing interface state density and improving channel mobility
Solution Approach 2:
The gate structure is segmented into multiple functional layers: amorphous carbon capping layer, silicon dioxide layer, and interface treatment layer. This segmentation allows each layer to perform its specific function optimally, with the carbon layer protecting against contamination and the oxide layer providing electrical isolation
Solution Approach 3:
The amorphous carbon layer acts as an intermediary between the SiC substrate and the silicon dioxide layer. It serves as a hard mask during etching, a capping layer during annealing, and a protective barrier that prevents direct interaction between SiC and oxide formation processes, thereby reducing interface states
2Reliability
If high-temperature annealing (>1800°C) is applied, then dopant activation and defect removal are improved, but process complexity and energy consumption increase
Solution Approach 1:
The annealing temperature is increased to extreme values (>1800°C) to achieve complete dopant activation and defect removal in the SiC substrate. This parameter change enables full utilization of dopant atoms and eliminates crystal defects that would otherwise degrade device performance
Solution Approach 2:
The high-temperature annealing process simultaneously performs multiple functions: activating dopants, removing defects, and stabilizing the amorphous carbon capping layer. This multi-functionality justifies the high energy input by achieving multiple critical objectives in a single process step
3Manufacturing precision
If amorphous carbon layer is used as hard mask, then etching selectivity is improved, but additional deposition and removal steps are required
Solution Approach 1:
The amorphous carbon layer provides locally enhanced etching resistance at the SiC surface, creating high etching selectivity between the carbon mask and the SiC substrate. This local quality difference enables precise trench formation while protecting surrounding areas
Solution Approach 2:
The amorphous carbon layer serves multiple functions simultaneously: it acts as a capping layer during annealing, a hard mask during etching, and a protective barrier during oxide deposition. By merging these functions into a single layer, the total number of process steps is reduced despite the added complexity of carbon layer management
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases channel mobility and transistor performance by reducing carbon clusters and interface state density, improving the reliability of SiC power devices under various high-temperature and high-stress conditions.
Implementation Method 1
depositing an amorphous carbon layer on a silicon carbide layer of the gate structure on the substrate to form a capping layer on the silicon carbide layer
Implementation Method 2
annealing the silicon carbide layer at a temperature of greater than approximately 1800 degrees Celsius
Implementation Method 3
etching the trench structure into the silicon carbide layer using a selective etch process with a higher etch rate of silicon carbide than amorphous carbon
Implementation Method 4
depositing a silicon dioxide layer of the gate structure on the silicon carbide layer using an atomic layer deposition process
Implementation Method 5
performing at least one interface treatment on the silicon dioxide layer including high temperature, oxygen/nitrogen radical treatment
Data Source
AI summary
A method of forming a gate structure on a substrate with increased charge mobility. In some embodiments, the method may include depositing an amorphous carbon layer on a silicon carbide layer on the substrate to form a capping layer on the silicon carbide layer, annealing the silicon carbide layer at a temperature of greater than approximately 1800 degrees Celsius, forming a hard mask on the silicon carbide layer by patterning the amorphous carbon layer, etching a trench structure of the gate structure into the silicon carbide layer using the hard mask, removing the hard mask to expose the silicon carbide layer, depositing a silicon dioxide layer on the silicon carbide layer using an ALD process, performing at least one interface treatment on the silicon dioxide layer, depositing a gate oxide layer of the gate structure on the silicon dioxide layer, and depositing a gate material on the gate oxide layer.