SiC Power Semiconductor Gate Structure for Lower Channel Resistance
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Solution Overview
Problem
Power semiconductor devices using silicon carbide (SiC) face challenges with increased threshold voltage and channel resistance due to negative charge traps at the gate interface, limiting channel density and breakdown voltage.
Innovation Solution
A hybrid-type structure incorporating trench-type and planar-type gate structures, with well regions surrounding trenches and pillar regions forming super junctions to enhance channel density and reduce electric field concentration, while counter-doping and JFET resistance are reduced through impurity implantation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon carbide (SiC) is used instead of silicon (Si) to maintain stability at higher temperatures and voltages, then temperature stability and breakdown voltage are improved, but negative charge traps at the gate interface increase threshold voltage and channel resistance
Solution Approach 1:
The patent applies local quality by creating distinct regions with different doping types (n-type drift region, p-type well regions) at specific locations within the semiconductor structure. The well regions are strategically positioned to compensate for interface trap effects locally at the gate interface, while the drift region maintains high voltage blocking capability. This localized doping strategy addresses the threshold voltage issue without compromising the overall temperature stability and breakdown voltage characteristics of the SiC material.
2Reliability
If silicon carbide (SiC) is used instead of silicon (Si) to maintain stability at higher temperatures and voltages, then temperature stability and breakdown voltage are improved, but channel resistance is increased
Solution Approach 1:
The patent implements local quality by forming p-type well regions at specific locations within the n-type drift region, creating localized areas with different electrical properties. These well regions are positioned to influence the channel characteristics directly, reducing channel resistance through controlled doping profiles while maintaining the high voltage blocking capability of the overall SiC structure.
Solution Approach 2:
The patent applies parameter changes by varying the doping concentration and type in different regions of the semiconductor structure. The drift region maintains low doping concentration for high voltage blocking, while well regions introduce higher concentration p-type doping to modulate the channel properties. This parameter variation allows optimization of both channel resistance and breakdown voltage in different spatial zones of the device.
3Ease of manufacture
If existing planar or trench structures are used, then manufacturing is simplified, but channel density cannot be increased
Solution Approach 1:
The patent applies segmentation by dividing the gate structure into multiple components: a planar gate electrode, vertically extending trenches, and p-type well regions positioned between trenches. This segmented approach allows each component to be formed using relatively simple processes while collectively achieving high channel density through the three-dimensional arrangement of multiple gate-controlled channels.
Solution Approach 2:
The patent implements dimensionality change by transitioning from a traditional two-dimensional planar gate structure to a three-dimensional structure with vertically extending trenches and laterally positioned well regions. This adds depth and spatial complexity to the gate control, enabling multiple channels to be formed in different spatial zones (under the planar gate, in trench regions, and at well region interfaces) without significantly complicating the manufacturing process.
Data Source
AI summary
A power semiconductor device includes an SiC semiconductor layer, a plurality of well regions disposed in the semiconductor layer such that two adjacent well regions at least partially make contact with each other, a plurality of source regions on the plurality of well regions in the semiconductor layer, a drift region in a first conductive type, a plurality of trenches recessed into the semiconductor layer from the surface of the semiconductor layer, a gate insulating layer on an inner wall of each trench, a gate electrode layer disposed on the gate insulating layer and including a first part disposed in each trench and a second part on the semiconductor layer, and a pillar region positioned under the plurality of well regions to make contact with the drift region and the plurality of well regions in the semiconductor layer, and having a second conductive type.