SiC MOSFET Gate Dielectric Stack for Low Interface State Density
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Solution Overview
Problem
Current silicon carbide (SiC) MOSFET devices face challenges with high on-state resistance and threshold voltage instability due to the limitations of silicon oxide gate dielectrics, which require high-temperature annealing and result in disordered interfaces and high electric field stress, leading to poor reliability and leakage current issues.
Innovation Solution
A multilayer gate dielectric stack comprising silicon oxide, hafnium oxide, and aluminum oxide layers is used, with specific thickness and bandgap configurations to create a high-density electron trap layer, reducing thermal budget and enhancing dielectric reliability, while maintaining low on-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon oxide (SiO2) is used as gate dielectric with thermal oxidation, then ease of manufacture is improved, but interface state density increases and channel mobility decreases
Solution Approach 1:
The patent applies composite materials by creating a multilayer gate dielectric stack comprising silicon oxide (SiO2), hafnium oxide (HfO2), and aluminum oxide (Al2O3) layers. This composite structure combines the manufacturing ease of SiO2 with the high-k properties of HfO2 and Al2O3, achieving low interface state density while maintaining ease of manufacture through sequential deposition processes.
Solution Approach 2:
The gate dielectric is segmented into multiple functional layers: a thin SiO2 layer (5-10 nm) providing interface quality, a HfO2 layer (5-20 nm) providing high-k dielectric properties, and an Al2O3 layer (5-20 nm) providing additional dielectric strength and interface passivation. Each layer performs a specific function to collectively solve the contradiction.
2Manufacturing precision
If high-temperature annealing is performed to reduce interface state density, then interface quality improves, but manufacturing time and thermal budget increase
Solution Approach 1:
The patent performs preliminary action by depositing the gate dielectric layers at optimized thicknesses and compositions that inherently provide low interface state density, reducing or eliminating the need for subsequent high-temperature annealing steps. The layered structure is designed to self-passivate interfaces without requiring extended thermal processing.
Solution Approach 2:
The patent changes parameters by optimizing the thickness and material composition of each layer in the gate dielectric stack. By controlling the thickness of SiO2 (5-10 nm), HfO2 (5-20 nm), and Al2O3 (5-20 nm) layers, the interface state density is reduced through material selection and structural design rather than through high-temperature annealing, thereby reducing manufacturing time.
3Ease of manufacture
If silicon oxide gate dielectric is used, then ease of manufacture is improved, but threshold voltage stability deteriorates under high electric field
Solution Approach 1:
The patent uses composite materials with high-k dielectric properties (HfO2 with k≈25, Al2O3 with k≈10) combined with SiO2 to create a gate dielectric stack that maintains electrical stability under high electric fields. The high-k materials provide superior dielectric strength and threshold voltage stability compared to SiO2 alone, while the composite structure maintains ease of manufacture through standard deposition techniques.
4Loss of energy
If on-state resistance is decreased, then power loss is reduced, but threshold voltage decreases
Solution Approach 1:
The patent changes parameters by optimizing the gate dielectric stack composition and thickness to achieve high channel mobility and low on-state resistance while maintaining stable threshold voltage. The high-k materials enable better electric field control, allowing independent optimization of on-resistance and threshold voltage through parameter tuning of the dielectric layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases the threshold voltage and reduces on-state resistance, improving channel mobility and stability, and provides higher capacitance and reduced ringing phenomena in MOSFET devices.
Implementation Method 1
A multilayer gate dielectric stack comprising silicon oxide, hafnium oxide, and aluminum oxide layers is used, with specific thickness and bandgap configurations to create a high-density electron trap layer
Implementation Method 2
The properties of the gate dielectric (permittivity, fixed charges, etc.) and the dielectric/SiC interface quality have a significant impact on relevant parameters of the MOSFET
Data Source
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AI summary
Electronic device (20; 60) comprising: a semiconductor body (48; 68), in particular of Silicon Carbide, SiC, having a first (48a; 68a) and a second face (48b; 68b), opposite to each other along a first direction (Z); and an electrical terminal (G; 82, 74) at the first face (48b; 68b), insulated from the semiconductor body (48; 68) by an electrical insulation region (52; 80). The electrical insulation region is a multilayer comprising: a first insulating layer (102), of a Silicon Oxide, in contact with the semiconductor body; a second insulating layer (104) on the first insulating layer (102), of a Hafnium Oxide; and a third insulating layer (106) on the second insulating layer (104), of an Aluminum Oxide.