Multi-Layer Gate Dielectric for SiC MOSFET Interface Trap Reduction
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Solution Overview
Problem
Metal-oxide-semiconductor field-effect transistors using silicon carbide substrates face degradation in electrical properties due to interface traps formed during thermal oxidation, which lowers carrier mobility.
Innovation Solution
A structure for a field-effect transistor is developed with a semiconductor substrate of wide bandgap material, featuring a first gate dielectric layer of silicon dioxide or aluminum oxide and a second gate dielectric layer of silicon dioxide, where the second layer is thicker and formed through thermal oxidation or high-temperature deposition, reducing interface traps and improving carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thermal oxidation process is used to form gate dielectric layer on silicon carbide substrate, then silicon dioxide layer is formed, but carbon is incorporated from substrate resulting in interface traps and degradation of electrical properties
Solution Approach 1:
The gate dielectric structure is segmented into multiple layers: a first gate dielectric layer formed by deposition and a second gate dielectric layer formed by thermal oxidation. This segmentation allows the harmful carbon incorporation to be confined to the second layer while the first layer provides a clean interface with the silicon carbide substrate, thereby reducing overall interface trap density.
Solution Approach 2:
The first gate dielectric layer acts as an intermediary layer between the silicon carbide substrate and the second gate dielectric layer. This intermediary layer prevents direct carbon incorporation into the oxide layer during thermal oxidation, as the deposition process creates a barrier that reduces carbon diffusion from the substrate.
2Reliability
If single layer gate dielectric structure is used, then manufacturing is simpler, but interface trap density is high due to carbon incorporation
Solution Approach 1:
The gate dielectric is divided into two functional layers with distinct formation processes and purposes. The first layer (deposited) provides a high-quality interface with low carbon contamination, while the second layer (thermally grown) provides excellent dielectric properties. This segmentation resolves the contradiction by improving carrier mobility through reduced interface traps despite increased structural complexity.
Solution Approach 2:
The gate dielectric structure uses a composite approach combining two different materials/formations: a deposited silicon dioxide or aluminum oxide layer combined with a thermally grown silicon dioxide layer. This composite structure leverages the advantages of both formation methods while mitigating their individual disadvantages, achieving low interface trap density and high carrier mobility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-layer gate dielectric structure reduces interface trap density, enhancing carrier mobility and electrical properties of the transistor, thereby improving the reliability and efficiency of high-power applications.
Implementation Method 1
The first gate dielectric layer may comprise silicon dioxide or aluminum oxide deposited by atomic layer deposition; the first gate dielectric layer may be deposited at a substrate temperature in a range between 25°C and 400°C
Implementation Method 2
The method step of forming the second gate dielectric layer on the first gate dielectric layer may comprise depositing a layer comprising silicon on the first gate dielectric layer, and oxidizing the layer with a thermal oxidation process to form the second gate dielectric layer
Implementation Method 3
the method may further comprise annealing the first gate dielectric layer and the second gate dielectric layer in an ambient including nitric oxide at a substrate temperature in a range between 1100°C and 1350°C
Data Source
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AI summary
Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor substrate comprising a wide bandgap semiconductor material, a gate electrode, a first gate dielectric layer disposed on the semiconductor substrate, and a second gate dielectric layer disposed between the first gate dielectric layer and the gate electrode.