Deposited Gate Dielectric Stack for SiC MOSFET Interface Traps

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Solution Overview

Problem

Metal-oxide-semiconductor field-effect transistors using silicon carbide substrates face degradation in electrical properties due to interface traps formed during thermal oxidation, which lowers carrier mobility in the inversion layer.

Innovation Solution

A structure for a field-effect transistor is formed with a semiconductor substrate of wide bandgap material, featuring a first gate dielectric layer and a second gate dielectric layer disposed between the first layer and the gate electrode, deposited using atomic layer deposition and chemical vapor deposition techniques to minimize carbon incorporation and reduce interface traps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If thermal oxidation process is used to form gate dielectric layer on silicon carbide substrate, then silicon dioxide layer is formed, but carbon is incorporated from substrate into the oxide layer resulting in interface traps and degradation of electrical properties

Engineering Contradiction:
Improveelectrical properties of gate dielectric layerVSAvoidinterface traps
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent extracts and removes the problematic thermal oxidation process that causes carbon incorporation. Instead of using thermal oxidation to form the gate dielectric layer, the invention deposits silicon dioxide or other dielectric materials using alternative methods such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), thereby eliminating the source of interface traps while maintaining the necessary insulating function of the gate dielectric layer

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the fundamental parameters of the gate dielectric formation process. Rather than using thermal oxidation at high temperatures that cause carbon diffusion into the oxide, the invention employs deposition processes with controlled temperature and chemistry parameters that prevent carbon incorporation, thus forming a clean interface between the gate dielectric and silicon carbide substrate

Inventive Principle:
Principle #35Parameter changes

2Reliability

If thermal oxidation is used to form gate dielectric, then silicon dioxide layer is created, but carrier mobility in inversion layer is lowered due to interface traps

Engineering Contradiction:
Improvecarrier mobilityVSAvoidinterface traps in inversion layer
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The invention removes the thermal oxidation step that generates interface traps, thereby eliminating the harmful factor that degrades carrier mobility in the inversion layer. The alternative deposition methods create a cleaner interface that does not introduce the same level of interface states

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent employs composite gate dielectric structures, such as combining silicon nitride and silicon oxide layers, or using silicon dioxide deposited by CVD/ALD methods. These composite or alternatively-deposited structures provide both the necessary electrical insulation and a clean interface that preserves high carrier mobility in the inversion layer

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The multiple gate dielectric layers reduce interface trap density, enhancing carrier mobility and maintaining high electrical properties by limiting carbon incorporation and optimizing substrate temperatures for deposition.

Implementation Method 1

deposited using atomic layer deposition and chemical vapor deposition techniques

Methodology Applied
Scientific EffectAtomic layer deposition: Physical Vapour Deposition

Implementation Method 2

deposited using atomic layer deposition and chemical vapor deposition techniques

Methodology Applied
Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Implementation Method 3

a gate dielectric layer that contains silicon dioxide formed by thermal oxidation process of the silicon carbide substrate

Methodology Applied
Scientific EffectThermal oxidation: Oxidation

Data Source

PatentUS20240290879A1Field-effect transistors with deposited gate dielectric layers
Publication Date: 2024.08.29 GLOBALFOUNDRIES US INC
  • US20240290879A1 patent drawing
  • US20240290879A1 patent drawing
  • US20240290879A1 patent drawing

AI summary

Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor substrate comprising a wide bandgap semiconductor material, a gate electrode, a first gate dielectric layer disposed on the semiconductor substrate, and a second gate dielectric layer disposed between the first gate dielectric layer and the gate electrode.