Multi-Level SiC MOSFET Gate Driver for Overshoot Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional gate drivers for SiC MOSFETs in high voltage applications face issues with overshoot current, overshoot voltage, dv/dt, and di/dt, leading to noise and device damage, while also reducing switching speed and not fully utilizing the characteristics of SiC MOSFETs.
Innovation Solution
A multi-level gate driver circuit is designed for SiC MOSFETs, comprising an SiC MOSFET information detection circuit, signal level shifting circuit, and segmented driving circuit, which includes turn-on and turn-off segmented driving circuits to manage switching speed, dv/dt, di/dt, and overshoot current and voltage, reducing parasitic effects and optimizing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a series of resistors is used at SiC MOSFET's gate to slow down driving current, then overshoot current and voltage are reduced, but switching speed is greatly reduced
Solution Approach 1:
The gate driver is divided into multiple levels (three-level structure with voltage nodes at 0V, VDD/2, and VDD) with separate driving circuits for each segment. This allows independent control of charging currents at different voltage stages, enabling reduced overshoot while maintaining fast switching speed through optimized current paths for each segment.
Solution Approach 2:
The gate driver uses dynamic control of driving currents through separate control signals for each voltage segment. The driving current is dynamically adjusted based on the real-time voltage state of the SiC MOSFET gate, allowing optimal current magnitude at each charging stage to balance switching speed and overshoot reduction.
2Speed
If active gate driver is adopted to maintain switching speed, then switching speed is maintained, but parasitic effect increases due to PCB implementation
Solution Approach 1:
The gate driver circuit is fully integrated onto a single chip with the SiC MOSFET, merging the power device and driving circuit into one unified structure. This integration eliminates external PCB connections, thereby reducing parasitic inductance and resistance while maintaining fast switching performance.
Solution Approach 2:
The gate driver is nested within the SiC MOSFET package structure, with the driving circuit physically embedded inside or adjacent to the power device. This nested configuration minimizes the loop area and parasitic elements by placing the driver as close as possible to the power device it controls.
Data Source
AI summary
A multi-level gate driver applied to the SiC metal-oxide-semiconductor field-effect transistor (MOSFET) includes three parts: the SiC MOSFET information detection circuit, the signal level shifting circuit, and the segmented driving circuit. The SiC MOSFET information detection circuit includes the SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit. The segmented driving circuit includes a turn-on segmented driving circuit and a turn-off segmented driving circuit. The SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit process a drain-source voltage and a drain-source current during the SiC MOSFET's switching as enable signals for segmented driving; the signal level shifting circuit transfers enable signals required by the segmented driving circuit to the suitable power supply rail; and the SiC MOSFET turn-on segmented driving circuit and the turn-off segmented driving circuit select suitable driving currents.