SiC Gate Edge Layout With Local Lifetime Control at Active Corners
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Solution Overview
Problem
Conventional silicon carbide semiconductor devices face challenges with high parasitic resistance components due to deep energy levels of aluminum used as a p-type impurity, leading to dielectric breakdown of the gate insulating film, especially at corners of the active region.
Innovation Solution
The introduction of a low carrier lifetime region with carrier lifetime killers in the corner portions of the intermediate region adjacent to the active region helps to shorten the average time for holes to disappear, reducing hole density and current concentration, thereby suppressing potential increases in the p-type regions and preventing dielectric breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If aluminum is used as a p-type impurity in the intermediate region, then the electrical conductivity is improved, but the deep energy level causes high parasitic resistance and dielectric breakdown of the gate insulating film
Solution Approach 1:
The patent introduces a low carrier lifetime region specifically in the corner portions of the intermediate region, creating local quality differences. This region has different carrier lifetime characteristics compared to other areas, allowing targeted suppression of hole accumulation at critical corners where dielectric breakdown is most likely to occur, without affecting the overall electrical conductivity provided by aluminum doping throughout the intermediate region.
Solution Approach 2:
The patent changes the carrier lifetime parameter in specific regions by introducing carrier lifetime killers. This parameter change reduces the average time for holes to disappear in the low carrier lifetime region, thereby reducing hole density and current concentration at corner portions, which suppresses potential increases in p-type regions and prevents dielectric breakdown.
2Reliability
If gate resistance is increased to prevent dielectric breakdown, then the reliability is improved, but the switching loss increases and cost-effectiveness deteriorates
Solution Approach 1:
Instead of uniformly increasing gate resistance throughout the device, the patent applies local quality modification by introducing low carrier lifetime regions specifically at corner portions. This localized approach reduces hole accumulation only where dielectric breakdown is most likely to occur, allowing the gate resistance to remain low and switching loss to be minimized while still improving reliability.
3Reliability
If chip size is increased to reduce current density, then the dielectric breakdown capability is improved, but the manufacturing cost increases
Solution Approach 1:
The patent employs local quality modification by introducing low carrier lifetime regions only in the corner portions of the intermediate region, rather than uniformly modifying the entire chip. This targeted approach reduces hole density and current concentration at critical locations, improving dielectric breakdown capability without requiring an increase in overall chip size, thereby maintaining cost-effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the dielectric breakdown capability of the gate insulating film, improves switching characteristics by reducing switching loss, and avoids the need for increasing gate resistance or chip size, thus maintaining cost-effectiveness.
Implementation Method 1
The introduction of a low carrier lifetime region with carrier lifetime killers in the corner portions of the intermediate region adjacent to the active region helps to shorten the average time for holes to disappear
Implementation Method 2
enhances the dielectric breakdown capability of the gate insulating film, improves switching characteristics by reducing switching loss
Data Source
AI summary
In an intermediate region surrounding a periphery of an active region, a gate polysilicon wiring layer is provided on a gate insulating film at a front surface of a semiconductor substrate, via a field oxide film. An inner end portion of the gate polysilicon wiring layer faces a p-type region of a surface region at the front surface of the semiconductor substrate, via only the gate insulating film. In the intermediate region, at corners thereof facing corners of the active region, a low carrier lifetime region containing a carrier lifetime killer is provided so as to overlap the p-regions and, in a depth direction, face the gate polysilicon wiring layer, whereby the lifetime of the minority carriers of the corner portions of the intermediate region is shorter than the lifetime of the minority carriers of linear portions of the intermediate region.