SiC Gate Insulator Layout for Low Resistance and Fast Switching
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Solution Overview
Problem
Power semiconductor devices based on silicon carbide (SiC) face challenges in achieving improved switching behavior due to interface trap states and defects at the gate dielectric/SiC interface, which degrade inversion channel mobility and increase resistance, while high-k gate dielectrics provide higher carrier density but slower switching speeds.
Innovation Solution
A power semiconductor device with a gate insulator having varying dielectric capacitance, comprising high-k material regions with larger capacitance at edges and lower capacitance in the central region, allowing for lower resistance and faster switching times without slowing down the device, by using a two-zone gate insulator design with different materials and thicknesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-k gate dielectric is used to increase carrier density, then the resistance in on-state is reduced, but the switching speed becomes slower
Solution Approach 1:
The gate insulator is divided into multiple regions with different dielectric materials: a first region with high-k material (e.g., HfO2, Al2O3) positioned at the edges where higher carrier density is needed to reduce on-state resistance, and a second region with lower-k material (e.g., SiO2) in the central area to maintain faster switching speed. This spatial segmentation allows simultaneous optimization of both resistance and switching characteristics.
Solution Approach 2:
Different regions of the gate insulator are assigned different dielectric properties tailored to their specific functional requirements. The high-k material is localized at edge regions where maximum electric field enhancement is beneficial for carrier injection, while the low-k material is placed in the central region where excessive capacitance would slow switching. This local quality differentiation resolves the contradiction between resistance reduction and switching speed maintenance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The described gate insulator structure reduces gate capacitance, maintaining lower resistance in the on-state and achieving shorter switching times, making it suitable for low to high voltage applications, including traction systems.
Implementation Method 1
The gate insulator has a varying dielectric capacitance which is, for example, larger at edges than in a central region
Implementation Method 2
a gate insulator that may fully or partially comprise a high-k material
Data Source
AI summary
In at least one embodiment, the power semiconductor device 1) involves a semiconductor body (2), at least one source region (21) in the semiconductor body (2), a gate electrode (3) at the semiconductor body (2), a gate insulator (4, 41, 42) between the semiconductor body (2) and the gate electrode (3), and at least one well region (22) at the at least one source region (21) and at the gate insulator (4, 41, 42), wherein the gate insulator (4, 41, 42) has a varying dielectric capacitance, the dielectric capacitance is in each case a quotient of a dielectric constant and of a geometric thickness of the gate insulator (4, 41, 42) at a specific location thereof, and the dielectric capacitance is larger at the at least one well region (22) than in remaining regions of the gate insulator (4, 42).