SiC Power Semiconductor Annealing for Stable Gate Interfaces
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Solution Overview
Problem
Existing power semiconductor devices face challenges in achieving improved electrical characteristics, particularly in high voltage and high current environments, due to limitations in voltage resistance and high-speed switching operations.
Innovation Solution
A manufacturing method for power semiconductor devices involving the formation of a substrate structure with specific conductivity-type layers, followed by annealing processes using nitrogen monoxide (NO) and deuterium (D), and high-pressure annealing to stabilize the interface between silicon carbide (SiC) and gate insulating layers, enhancing the stability and performance of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional manufacturing methods are used for power semiconductor devices, then the manufacturing process is simpler, but the electrical characteristics (breakdown voltage, threshold voltage, sub-threshold swing) are insufficient
Solution Approach 1:
The patent applies preliminary action by performing multiple annealing processes at specific stages before final device completion. The first annealing process is performed after forming the substrate structure but before forming the gate insulating layer, the second annealing process is performed after forming the preliminary gate insulating layer, and the high-pressure annealing process is performed after forming the gate insulating layer and gate electrode. These preliminary treatments prepare the silicon carbide substrate and interfaces in advance to achieve improved electrical characteristics throughout the device lifecycle.
Solution Approach 2:
The patent applies parameter changes by varying temperature, pressure, and atmospheric composition across different annealing processes. The first annealing uses temperatures of 1000-1500°C in nitrogen or oxygen atmosphere, the second annealing uses 800-1200°C in nitrogen monoxide atmosphere, and the high-pressure annealing uses 300-600°C at pressures of 1-100 atm in deuterium atmosphere. These parameter variations optimize the electrical characteristics at different manufacturing stages.
2Strength
If high voltage resistance is achieved through material selection (SiC), then voltage resistance improves, but manufacturing complexity increases due to multiple specialized annealing processes
Solution Approach 1:
The patent performs preliminary annealing treatments to prepare the silicon carbide substrate and create optimized interfaces before final device assembly. The first annealing process prepares the substrate structure, the second annealing process prepares the gate insulating layer interface, and the high-pressure annealing process finalizes the interface stability. These preliminary actions ensure the SiC material achieves its full voltage resistance potential without requiring overly complex final assembly procedures.
Solution Approach 2:
The patent utilizes parameter changes in the annealing processes to enhance the inherent voltage resistance of silicon carbide. By controlling temperature (1000-1500°C for first annealing, 800-1200°C for second annealing, 300-600°C for high-pressure annealing), pressure (1-100 atm for high-pressure annealing), and atmosphere composition (nitrogen, oxygen, nitrogen monoxide, deuterium), the material's electrical properties are optimized to maximize voltage resistance while managing process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in improved breakdown voltage, decreased threshold voltage, and reduced sub-threshold swing, leading to enhanced electrical characteristics and stability of the power semiconductor devices.
Implementation Method 1
performing a first annealing process on the substrate structure
Implementation Method 2
performing a second annealing process on the substrate structure and the preliminary gate insulating layer using nitrogen monoxide (NO)
Implementation Method 3
performing a high-pressure annealing process using deuterium (D)
Data Source
AI summary
A method of manufacturing a power semiconductor device includes forming a drift layer, a well region, and a source region to form a substrate structure, forming mask layers on upper and lower surfaces of the substrate structure, performing a first annealing process on the substrate structure, forming a preliminary gate insulating layer on the upper surface of the substrate structure, performing a second annealing process on the substrate structure, forming a preliminary gate electrode layer on the preliminary gate insulating layer, forming a gate insulating layer and a gate electrode layer, forming a dielectric layer on the gate electrode layer, forming a source electrode coupled with the source region, forming a drain electrode on the lower surface of the substrate, and performing a high-pressure annealing process using deuterium subsequent to at least one of the performing the second annealing process or the forming of the dielectric layer.