SiC Gate Electrode Structure for Higher Mobility and Threshold Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing SiC semiconductor devices face challenges in improving channel mobility while maintaining high threshold voltage and reducing off-leakage current due to imbalances in impurity concentration and crystal orientation, leading to defects and reduced withstand voltage.
Innovation Solution
Employing P-type Poly-SiC as the gate electrode material with a Fermi level closer to the Fermi level of the semiconductor region, and using a SiC substrate with an off-angle less than 4° to align gate trench side surfaces parallel to the (11-20) plane, thereby reducing energy band bending and enhancing channel mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the P-type impurity concentration near the surface of the body region is lowered to improve channel mobility, then channel mobility is improved, but the threshold voltage falls and off-leakage current increases
Solution Approach 1:
The patent applies local quality by creating distinct impurity concentration zones within the body region. The surface portion has low P-type impurity concentration (≤1×10^18 cm^-3) to improve channel mobility, while deeper portions maintain higher concentrations to ensure adequate threshold voltage. This spatial differentiation of impurity concentrations allows simultaneous optimization of both channel mobility and threshold voltage characteristics.
Solution Approach 2:
The patent transitions from uniform impurity concentration to depth-dependent impurity concentration distribution. By controlling the vertical profile of P-type impurities through selective epitaxial growth and doping processes, the invention creates a three-dimensional impurity distribution that optimizes electrical characteristics at different depths, effectively resolving the contradiction between surface mobility and overall device threshold voltage.
2Speed
If the off-angle of the SiC substrate is increased to align gate trench side surfaces parallel to the (11-20) plane for improved channel mobility, then channel mobility is improved, but manufacturing precision and uniformity deteriorate
Solution Approach 1:
The patent optimizes the off-angle parameter of the SiC substrate to a specific range (0.3° to 4°) that balances channel mobility improvement with manufacturing precision. This parameter optimization ensures that the gate trench side surfaces are sufficiently aligned with the (11-20) plane to achieve high electron mobility while maintaining practical manufacturability and uniformity across wafers.
3Reliability
If the P-type impurity concentration in the body region is increased to raise the threshold voltage, then the threshold voltage is raised, but channel mobility deteriorates
Solution Approach 1:
The patent applies local quality by creating distinct impurity concentration zones within the body region. The surface portion has low P-type impurity concentration (≤1×10^18 cm^-3) to improve channel mobility, while deeper portions maintain higher concentrations to ensure adequate threshold voltage. This spatial differentiation of impurity concentrations allows simultaneous optimization of both channel mobility and threshold voltage characteristics.
Solution Approach 2:
The patent transitions from uniform impurity concentration to depth-dependent impurity concentration distribution. By controlling the vertical profile of P-type impurities through selective epitaxial growth and doping processes, the invention creates a three-dimensional impurity distribution that optimizes electrical characteristics at different depths, effectively resolving the contradiction between surface mobility and overall device threshold voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach raises the threshold voltage, reduces off-leakage current, and improves channel mobility while maintaining dielectric breakdown strength and uniformity in channel characteristics.
Implementation Method 1
Employing P-type Poly-SiC as the gate electrode material with a Fermi level closer to the Fermi level of the semiconductor region, and using a SiC substrate with an off-angle less than 4° to align gate trench side surfaces parallel to the (11-20) plane, thereby reducing energy band bending and enhancing channel mobility
Data Source
AI summary
A semiconductor device includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film.