SiC Planar Transistor Gate Overlap for Shoot-Through Withstand
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Solution Overview
Problem
MOS-based SiC planar devices face challenges in shoot-through withstand capability due to high dV/dt transitions and voltage pulses caused by Miller capacitance feedback, which can lead to frequent switching issues and reduced performance, especially in devices with low gate threshold voltage.
Innovation Solution
The use of titanium carbide (TiC) source contacts and a planar gate structure with a gate dielectric that overlaps the source and source contact structures, along with a method of manufacturing that forms TiC contacts before gate structure formation, allowing for increased input capacitance and mitigating shoot-through by stabilizing the device at high temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOS-based SiC planar devices are used with low gate threshold voltage, then switching performance is improved, but shoot-through withstand capability deteriorates due to Miller capacitance feedback causing voltage pulses
Solution Approach 1:
The gate structure is extended in the planar dimension to overlap with the source contact structure, increasing the gate-to-source capacitance (Ciss) by utilizing additional overlapping area. This dimensional extension allows the gate to control a larger capacitance, thereby reducing the impact of Miller capacitance feedback and improving shoot-through withstand capability while maintaining low gate threshold voltage for good switching performance.
Solution Approach 2:
The capacitance ratio Crss/Ciss is changed by increasing Ciss through the extended gate overlap with the source contact. By modifying the geometric parameters of the gate structure (extending its length to overlap source contact), the input capacitance increases, which changes the overall capacitance ratio and reduces the severity of Miller effect, thereby improving reliability without sacrificing switching performance.
2Power
If high dV/dt transitions occur in power switching, then power handling capability is improved, but voltage pulses are induced through Miller capacitance feedback causing switching issues
Solution Approach 1:
The gate structure is extended in the planar dimension to overlap with the source contact structure, increasing the gate-to-source capacitance (Ciss). This increased input capacitance acts as a buffer that reduces the impact of Miller capacitance feedback during high dV/dt transitions, thereby suppressing voltage pulses while maintaining the power handling capability enabled by high dV/dt switching.
3Stability of the object's composition
If titanium carbide source contacts are used, then contact stability at high temperatures is improved, but manufacturing complexity increases due to additional processing steps
Solution Approach 1:
The titanium carbide source contact structure is formed before the gate structure in the manufacturing process. This preliminary formation allows the TiC contact to be established with proper crystalline orientation and electrical properties before subsequent gate processing steps, ensuring high-temperature stability while managing manufacturing complexity through optimized process sequencing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces the C_rss/C_iss capacitance ratio, enhancing the shoot-through withstand capability and stability of SiC transistor devices, even at high temperatures, by increasing the input capacitance and preventing voltage pulses, thus improving switching performance.
Implementation Method 1
increasing the input capacitance and mitigating shoot-through by stabilizing the device at high temperatures
Implementation Method 2
using titanium carbide having excellent crystalline matching with electrical contact with a source electrode and a second semiconductor layer
Implementation Method 3
mitigating shoot-through by stabilizing the device at high temperatures
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 2C~2D
AI summary
A silicon carbide (SiC) transistor device comprises a SiC semiconductor substrate (1) having a top surface, a SiC epitaxial layer (2) formed on the top surface of the SiC semiconductor substrate (1), the SiC epitaxial layer (2) having a top surface, a source structure formed in the top surface of the SiC epitaxial layer, the source structure having a top surface and comprising a p-well region (3), an n-type source region (4) and a p-type contact region (5), a channel region (10) and a source contact structure (9) formed over and electrically connected to the top surface of the source structure, wherein the source contact structure (9) comprises one of Titanium carbide (TiC), Tungsten carbide (WC) and Nickel carbide (NiC3), a planar gate structure including a gate dielectric (7) and a gate runner (6), wherein the gate dielectric (7) covers the channel region (10), at least part of the source structure and at least part of the source contact structure (9) and the gate runner (6), which is electrically insulated from the channel region (10) the source structure and the source contact structure (9) by the gate dielectric (7), overlaps the channel region (10) and at least part of the source contact structure (9).