SiC Power Semiconductor Structure for Gate Oxide Field Shifting
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Solution Overview
Problem
Existing power semiconductor devices, such as Schottky MOSFETs and IGBTs, face challenges in reliability due to peak electric fields that can lead to increased on-state resistance and reduced performance, particularly in silicon carbide (SiC) materials.
Innovation Solution
A power semiconductor device with a base layer of SiC and embedded zones of a second conductivity type that shift the peak electric field away from the gate oxide, utilizing a metal or polysilicon gate contact and high-K dielectric stacks, and strategically positioned contact layers to manage the electric field and improve current spreading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If Schottky contacts are used in power semiconductor devices, then excellent dynamic electrical parameters are achieved, but reliability is reduced due to peak electric fields at the gate oxide interface
Solution Approach 1:
The patent introduces a localized p-doped protection layer at the gate oxide interface region, creating a non-uniform doping structure. This local modification of the base layer's electrical properties reduces the peak electric field density at the critical gate oxide interface, thereby improving reliability without compromising the overall Schottky contact performance and dynamic electrical parameters.
Solution Approach 2:
The p-doped protection layer acts as an intermediary structure between the n-type base layer and the gate oxide. This intermediate layer with opposite conductivity type serves to redistribute and reduce the electric field peaks, protecting the gate oxide from high field stress while maintaining the beneficial low on-state resistance characteristics of Schottky contacts.
2Loss of energy
If the base layer has high doping concentration, then on-state resistance is reduced, but peak electric field increases leading to reliability issues
Solution Approach 1:
The patent creates a spatially varying doping concentration in the base layer by introducing a p-doped protection layer at the gate oxide interface. This local quality change allows the bulk base layer to maintain high doping concentration for low on-state resistance, while the interface region has modified electrical properties that reduce peak electric field and protect the gate oxide.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the reliability and reduces on-state resistance of the power semiconductor device by effectively managing the electric field and improving current spreading, while maintaining production efficiency and quality.
Implementation Method 1
the protection layer, which is p-doped, and which is in contact with the insulation layer, wherein a maximum doping concentration of the p-doped layer is larger than 10 18
Implementation Method 2
utilizing a metal or polysilicon gate contact and high-K dielectric stacks
Data Source
Figure 1~3
Figure 4~5
Figure 6~8
AI summary
A power semiconductor device (1) is specified comprising - an electrode (2); - a base layer (3) of a first conductivity type provided on the electrode (2); - at least one contact layer (4) provided on the base layer (3) ; - a gate contact (5) provided on the base layer (3) and on the at least one contact layer (4); - an insulation layer (6) between the gate contact (5) and the base layer (3) and between the at least one contact layer (4) and the gate contact (5), and - at least one zone (7) of a second conductivity type within the base layer (3), - wherein the at least one zone (7) is constructed and arranged to shift away a peak electric field generated in the base layer (3) from the insulation layer (6) between the gate contact (5) and the base layer (3). Furthermore, a method for producing a power semiconductor device is specified.