SiC Gate Oxide Interface Smoothing With an Implanted Silicon Layer

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Solution Overview

Problem

The interface between silicon carbide substrates and gate oxide layers in semiconductor devices is often rough, leading to degraded carrier mobility and limited device performance.

Innovation Solution

A method of fabricating semiconductor devices involves forming a silicon layer on a silicon carbide substrate and then creating a gate oxide layer by oxidizing the silicon layer. This process can include implanting silicon into the substrate to form a silicon rich layer, followed by epitaxial growth of additional silicon layers and oxidation to form the gate oxide layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a gate oxide layer is formed directly on a silicon carbide substrate, then the fabrication process is simple, but the interface becomes rough leading to degraded carrier mobility

Engineering Contradiction:
Improvefabrication process simplicityVSAvoidinterface quality
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

A silicon layer is introduced as an intermediary between the silicon carbide substrate and the gate oxide layer. This intermediate silicon layer serves as a buffer that enables the formation of a high-quality oxide interface while maintaining compatibility with the silicon carbide substrate, thus resolving the contradiction between process simplicity and interface quality.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The silicon layer is formed on the silicon carbide substrate before the gate oxide layer is deposited. This preliminary action prepares a suitable surface for oxide formation, ensuring that when the gate oxide is subsequently formed, it achieves a smooth interface and high quality without requiring complex in-situ processing during the oxide deposition step.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If carbon concentration is not controlled in the silicon layer, then the fabrication process is simpler, but defects increase reducing carrier mobility

Engineering Contradiction:
Improvefabrication process simplicityVSAvoidcarrier mobility
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The carbon concentration in the silicon layer is controlled and optimized as a key parameter. By adjusting the carbon concentration to specific ranges during silicon layer formation, the method achieves a balance between maintaining fabrication simplicity and ensuring high carrier mobility, as proper carbon control reduces defects while avoiding overly complex processing.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If the silicon layer thickness is increased to improve interface quality, then carrier mobility improves, but the fabrication complexity and defect risk increase

Engineering Contradiction:
Improveinterface qualityVSAvoidfabrication process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The silicon layer thickness is optimized to a specific range (100-5000 angstroms) to achieve the best interface quality. This parameter optimization ensures that the layer is thick enough to provide a smooth interface for gate oxide formation and improve carrier mobility, but not so thick as to introduce excessive fabrication complexity or defect risks.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The described method improves the quality of the interface between the silicon carbide substrate and the gate oxide layer, enhancing carrier mobility and overall device performance by reducing defects and optimizing the carbon concentration in the silicon layers.

Implementation Method 1

The step of forming the gate oxide layer may include oxidizing silicon from the silicon layer to form the gate oxide layer of silicon dioxide

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 2

implanting silicon into a silicon carbide substrate to form a first silicon rich layer

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 3

forming a second silicon layer over the first silicon layer using epitaxial growth

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS20250054761A1Semiconductor device and method for manufacturing same
Publication Date: 2025.02.13 MICROCHIP TECHNOLOGY INC
  • US20250054761A1 patent drawing
  • US20250054761A1 patent drawing
  • US20250054761A1 patent drawing

AI summary

A semiconductor device that may include a silicon carbide substrate, a silicon layer disposed on the silicon carbide substrate, and a gate oxide layer disposed on the silicon layer. The silicon layer may be implanted within the silicon carbide substrate. The silicon layer may comprise a thickness of 100 angstroms 5000 angstroms. The silicon layer may contain less than one percent carbon, or may contain a certain percentage of carbon that decreases as a distance from the surface of the silicon carbide substrate increases.