SiC Device Gate Oxide Reliability via Channel Length Shielding
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Solution Overview
Problem
The reliability of the gate oxide film in silicon carbide semiconductor devices is compromised due to high electric fields at the gate-electrode edges, particularly in high-speed switching operations, and existing methods are costly to address this issue.
Innovation Solution
The manufacturing method involves forming well regions, source regions, and channel regions using specific impurities that do not diffuse during activation annealing, and forming gate electrodes in a manner that the channel regions and gate electrodes have a length relationship (Lch < Lg < Lwell) to shield the electric field at the gate-electrode edges, ensuring the gate oxide film's reliability while minimizing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If gate electrodes are formed to reduce gate capacitance in high-speed switching operations, then switching speed and loss reduction are improved, but high electric fields are generated at gate-electrode edges causing reliability deterioration of the gate oxide film
Solution Approach 1:
A buffer region is introduced as an intermediary structure between the gate electrode and the depletion region. This buffer region, formed by ion-implanting aluminum at a lower concentration than the well region, acts as a mediator that reduces the electric field concentration at the gate-electrode edges. The buffer region's lower impurity concentration creates a gradual transition in the electric field distribution, preventing the high electric field peaks that would otherwise occur at the sharp edges of the gate electrode over the depletion region, thus protecting the gate oxide film from breakdown while maintaining high-speed switching capability
2Reliability
If conventional methods are used to address the high electric field problem at gate-electrode edges, then gate oxide film reliability is improved, but manufacturing cost increases significantly
Solution Approach 1:
The buffer region formation process is merged with the existing well region formation process. Both the well region and buffer region are formed through ion implantation of aluminum, but with different concentrations and spatial distributions. The buffer region uses the same ion implantation technology and activation annealing process as the well region, requiring no additional manufacturing equipment or fundamentally new process steps. This merging approach allows the electric field reduction function to be achieved while maintaining compatibility with conventional manufacturing processes, thereby avoiding significant cost increases
Solution Approach 2:
The invention changes the impurity concentration parameter of the aluminum-doped region to create the buffer effect. By implanting aluminum at a lower concentration (1×10^16 to 1×10^18 atoms/cm³) compared to the well region (1×10^17 to 1×10^19 atoms/cm³), the electric field distribution is modified. This parameter change in impurity concentration creates a gradual transition zone that reduces electric field peaks without requiring changes to the basic manufacturing process flow, thus achieving reliability improvement at acceptable manufacturing cost
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach relaxes the electric field at the gate-electrode edges, enhancing the reliability of the gate oxide film and reducing manufacturing costs by maintaining the conventional manufacturing steps with additional boron diffusion for channel formation, thus effectively addressing the reliability and cost concerns.
Implementation Method 1
the channel regions and the gate electrode have a length relationship (Lch < Lg < Lwell) to shield the electric field at the gate-electrode edges
Implementation Method 2
forming channel regions and the gate electrode have a length relationship (Lch < Lg < Lwell)
Implementation Method 3
forming well regions, source regions, and channel regions using specific impurities that do not diffuse during activation annealing
Data Source
AI summary
A manufacturing method of a silicon carbide semiconductor device in which an electric field applied to a gate oxide film can be relaxed and thereby reliability can be ensured, and by the method manufacturing costs can be reduced. Well regions, channel regions, and gate electrodes are formed so that, given that extending lengths, with respect to the inner sides of source regions, of each of the well regions, the channel regions, and the gate electrodes are Lwell, Lch, and Lg, respectively, a relationship of Lch<Lg<Lwell is satisfied; and the channel regions are further formed by diffusing by activation annealing boron as a third impurity, having been implanted by activation annealing into the source regions, into a silicon carbide layer.