SiC Gate Pad Layout for Wider Transistor Active Region
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Solution Overview
Problem
The existing semiconductor devices face a challenge in securing a wide actuation region due to the size requirements of the gate pad, which narrows the active region that can be actuated as a transistor, especially when wire bonding is involved.
Innovation Solution
A semiconductor device with a vertical type transistor using a SiC semiconductor layer, featuring a gate structure with an insulating layer, a gate main electrode, and a gate pad electrode that overlaps with both active and non-active regions, allowing for a larger active region while maintaining a sufficient gate pad size for wire bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate pad size is increased to accommodate wire bonding, then the reliability of electrical connection is improved, but the area of the active region is reduced
Solution Approach 1:
The gate pad electrode is extended in the vertical dimension to overlap with both the active and non-active regions in plan view. This three-dimensional configuration allows the gate pad to maintain sufficient size for wire bonding while minimizing the horizontal footprint over the active region, thus resolving the contradiction between connection reliability and active area.
Solution Approach 2:
The gate pad electrode is divided into multiple segments: a gate main electrode portion over the active region and a gate pad portion extending over the non-active region. This segmentation allows the different portions to serve different functions - the main electrode provides electrical connection to the active region while the pad portion provides mechanical support and wire bonding surface.
2Ease of manufacture
If the gate pad size is secured for wire bonding, then the ease of manufacture is improved, but the productivity of active region utilization is reduced
Solution Approach 1:
By extending the gate pad electrode vertically to overlap multiple regions in plan view, the design provides sufficient pad area for wire bonding operations without increasing the horizontal footprint over the active region, thus maintaining manufacturing ease while improving active region utilization.
Solution Approach 2:
The gate pad electrode has different functional zones: a smaller area directly over the active region for electrical connection and a larger overlapping area extending into the non-active region for wire bonding. This local differentiation optimizes both manufacturing ease and active region productivity.
Data Source
AI summary
A semiconductor device includes a semiconductor layer which has a main surface and includes SiC as a main component, a gate structure which is formed in the main surface, an insulating layer which is formed on the main surface such as to cover the gate structure, a gate main electrode which is arranged on the insulating layer and electrically connected to the gate structure, and a gate pad electrode which includes a connecting portion which is arranged on the gate main electrode such as to be connected to the gate main electrode and connected to the gate main electrode with a first area in plan view and an electrode surface having a second area exceeding the first area in plan view.