SiC Device Gate Pad Potential Management
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Solution Overview
Problem
Silicon carbide semiconductor devices face dielectric breakdown issues under the gate pad due to high resistance and deep impurity levels of aluminum or boron ions, making it difficult to suppress potential differences and prevent insulating film breakdown during switching.
Innovation Solution
A silicon carbide semiconductor device design featuring a semiconductor substrate with specific impurity regions, a gate insulating film, and a field insulating film, along with an interlayer insulating film, which includes a third impurity region with a higher impurity concentration to manage displacement currents and reduce potential differences under the gate pad.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a second well contact hole is used to suppress potential difference, then the potential difference under the gate pad is reduced, but for large gate pads or rapid switching, the potential difference cannot be sufficiently suppressed, leading to dielectric breakdown
Solution Approach 1:
The invention divides the potential difference suppression function into multiple components: the second well contact hole provides local suppression, while the third impurity region (outer peripheral region) provides extended suppression coverage. This segmentation allows the system to handle larger gate pads and faster switching by distributing the suppression function across multiple structured elements rather than relying on a single contact hole.
Solution Approach 2:
The invention extends the suppression mechanism from a vertical structure (second well contact hole reaching from surface to second well region) to include a horizontal dimension (third impurity region in the outer peripheral region). This dimensional extension allows displacement current to be suppressed across a broader area, effectively handling larger gate pads without increasing the complexity of individual components.
2Reliability
If the dose of Al or B is increased to reduce resistance, then the p-type region resistance is reduced, but the deep impurity level and difficult defect recovery prevent dose increase
Solution Approach 1:
The invention changes the doping concentration parameter across different regions: the third impurity region has a doping concentration specifically optimized for potential difference suppression during rapid switching, while other regions have concentrations optimized for their respective functions. This parameter differentiation allows the device to achieve low resistance where needed without violating the manufacturing constraints of Al or B ion implantation in silicon carbide.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively suppresses dielectric breakdown of the insulating film under the gate pad by managing displacement currents and reducing potential differences, enhancing the reliability of silicon carbide semiconductor devices.
Implementation Method 1
the voltage rise causes a displacement current to flow through both p-type and n-type impurity regions, thus producing a potential difference under the gate pad
Data Source
AI summary
A present invention includes the following: a third impurity region having a second conductivity type and disposed in an outer peripheral region that is the outer periphery of a cell arrangement region in which a unit cell is disposed; a field insulating film disposed in the outer peripheral region; an interlayer insulating film; a first main electrode disposed on the interlayer insulating film. The third impurity region includes a fourth impurity region having the second conductivity type, having a higher impurity concentration than the third impurity region. A gate wire and a gate pad are disposed in the outer peripheral region. The fourth impurity region is adjacent to the cell arrangement region, surrounds at least a region below the gate pad, and is electrically connected to the first main electrode.