Silicon Carbide Device Gate Resistance Reduction
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Solution Overview
Problem
Conventional silicon carbide semiconductor devices face challenges with increased chip size, where gate resistance variations lead to operational differences and constraints in wire bonding due to the need for a large gate runner area, which sacrifices active region space and complicates bonding positions.
Innovation Solution
A silicon carbide semiconductor device with a trench gate structure and a silicide layer in the polycrystalline silicon gate wiring trench, reducing gate resistance and area requirements, allowing for a more compact gate runner and improved wire bonding capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If chip size is increased, then current handling capability is improved, but gate resistance variation increases causing operational differences
Solution Approach 1:
The gate runner is divided into multiple gate wiring trenches filled with polycrystalline silicon, creating segmented low-resistance paths distributed across the chip. This segmentation allows current to flow through multiple parallel paths, reducing overall gate resistance while maintaining uniformity across large chip areas.
Solution Approach 2:
The gate wiring structure transitions from a planar surface configuration to a three-dimensional trench-based structure. By etching trenches into the semiconductor substrate and filling them with polycrystalline silicon, the gate wiring gains vertical dimension, increasing effective wiring area and reducing resistance without expanding chip footprint.
2Reliability
If a large gate runner area is provided, then gate resistance is reduced, but active region space is sacrificed
Solution Approach 1:
The gate wiring structure transitions from a planar surface configuration to a three-dimensional trench-based structure. By etching trenches into the semiconductor substrate and filling them with polycrystalline silicon, the gate wiring gains vertical dimension, increasing effective wiring area and reducing resistance without expanding chip footprint.
Solution Approach 2:
The gate runner utilizes a polycrystalline silicon-filled trench structure that effectively uses the vertical space within the substrate. This porous-like three-dimensional structure provides extensive wiring path area within the bulk material, reducing resistance without consuming additional surface area that would be available for active regions.
3Power
If chip size is increased, then power handling is improved, but wire bonding constraints increase due to bonding position limitations
Solution Approach 1:
The gate runner is divided into multiple gate wiring trenches filled with polycrystalline silicon, creating segmented low-resistance paths distributed across the chip. This segmentation allows current to flow through multiple parallel paths, reducing overall gate resistance while maintaining uniformity across large chip areas.
Data Source
AI summary
A semiconductor device includes an active region through which a main current passes during an ON state. In the active region, the semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, gate insulating films, gate electrodes, an interlayer insulating film, first electrodes, a second electrode, first trenches, a second trench, a polycrystalline silicon layer provided in the second trench via one of the gate insulating films, and a silicide layer selectively provided in a surface layer of the polycrystalline silicon layer. The polycrystalline silicon layer and the silicide layer are electrically connected with the gate electrodes.