SiC Gate Resistor Integration for Stable Gate Biasing
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Solution Overview
Problem
Existing silicon carbide power devices face inefficiencies due to unbalanced parallel coupling and high manufacturing costs when discrete resistances are used in series with gate contacts, leading to inefficiencies and variability in resistance values.
Innovation Solution
Integrate a doped region within the silicon carbide substrate to form an insulated series resistance before the gate contact, utilizing high-temperature activation steps to precisely control resistance values and minimize spread across wafers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If discrete resistances are mounted separately on printed circuits, then resistance values can be controlled, but manufacturing cost increases and resistance variability across wafers worsens
Solution Approach 1:
The patent merges the discrete resistance component with the silicon carbide substrate by fabricating the resistance directly within the substrate using doped regions. This integration eliminates the need for separate discrete resistance components and their associated mounting processes, thereby reducing manufacturing cost while improving resistance value consistency across wafers through unified fabrication.
Solution Approach 2:
The silicon carbide substrate serves multiple functions: it acts as both the power device substrate and the resistance element substrate. By doping specific regions of the silicon carbide material, the same substrate material provides both the power device functionality and the resistance functionality, eliminating the need for separate components and reducing overall manufacturing complexity.
2Adaptability or versatility
If discrete resistances are used for gate biasing, then resistance can be added to gate contacts, but device complexity and manufacturing steps increase
Solution Approach 1:
The resistance element is merged with the gate contact structure by forming doped regions within the silicon carbide substrate that are electrically connected to the gate contact. This integration allows gate biasing control to be achieved through the substrate itself rather than requiring separate discrete resistance components, thereby reducing device complexity while maintaining the desired electrical control functionality.
3Ease of manufacture
If polysilicon resistance is photolithographically defined, then resistance can be integrated within the die, but resistance value spread between wafers increases
Solution Approach 1:
The patent changes the material parameter from polysilicon to doped silicon carbide for the resistance element. This parameter change leverages the inherent material properties of silicon carbide and the precision of ion implantation/doping processes to achieve more consistent resistance values across wafers. The doped regions in silicon carbide provide better control over resistance characteristics compared to photolithographically defined polysilicon structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Achieves stable and controllable resistance values with low variability, improving efficiency and reliability of silicon carbide power devices without additional manufacturing steps.
Implementation Method 1
an integrated resistor (30) including a doped region (32) of a first conductivity type (N+), arranged at the front surface (4a) of said functional layer (4) in said edge area (2a), wherein said integrated resistor (30) is configured to define an insulated resistance in said functional layer (4)
Data Source
AI summary
A silicon carbide power device has: a die having a functional layer of silicon carbide and an edge area and an active area, surrounded by the edge area; gate structures formed on a top surface of the functional layer in the active area; and a gate contact pad for biasing the gate structures. The device also has an integrated resistor having a doped region, of a first conductivity type, arranged at the front surface of the functional layer in the edge area; wherein the integrated resistor defines an insulated resistance in the functional layer, interposed between the gate structures and the gate contact pad.