SiC Gate Interconnect Resistance Layout for Ringing Suppression
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Solution Overview
Problem
Existing power semiconductor devices face challenges in achieving high-voltage withstanding properties and high-speed switching operations, particularly in SiC-based devices, which can lead to undesirable ringing phenomena due to excessive switching speeds.
Innovation Solution
The design incorporates a high-resistance connector between the gate bus lines and the gate pad, adjusting the overall resistance of the gate interconnection structure to reduce switching speed and prevent ringing, while maintaining high electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed switching operation is implemented in SiC-based power semiconductor devices, then switching speed is improved, but ringing phenomena occur due to excessive switching speeds
Solution Approach 1:
A connector with intermediate resistivity is introduced between the gate bus line and gate pad to act as a mediator. This connector has resistivity higher than the gate bus line and gate pad but lower than the gate electrode, creating a graded resistance distribution that dampens oscillations and reduces ringing phenomena while preserving high-speed switching performance.
Solution Approach 2:
The resistivity parameter of the gate interconnection structure is optimized by selecting materials with specific resistivity ranges. The gate electrode uses high-resistivity material (20-100 μΩ·cm), the connector uses intermediate-resistivity material (5-20 μΩ·cm), and the gate bus line and pad use low-resistivity material (1-5 μΩ·cm), creating a parameter gradient that controls switching characteristics and suppresses ringing.
2Strength
If SiC material is used for high-voltage withstanding properties, then voltage blocking capability is improved, but device complexity increases due to additional structure requirements
Solution Approach 1:
Different regions of the gate interconnection structure are assigned different material properties and resistivity values to optimize local functions. The gate electrode region uses high-resistivity material for E-field control, the connector region uses intermediate-resistivity material for damping, and the bus line/pad regions use low-resistivity material for current conduction, achieving high-voltage withstanding capability through localized material optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the electrical properties of power semiconductor devices by reducing switching speed and preventing ringing, enhancing suitability for commercial packages and modules.
Implementation Method 1
gate insulating layers in gate trenches penetrating the source regions and the well region and extending in a first direction parallel to an upper surface of the substrate, and including a high-κ material
Implementation Method 2
a connector electrically connecting the gate bus line to the gate pad and having a resistivity greater than those of the gate bus line and the gate pad
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
A power semiconductor device includes a substrate having a first conductivity type and being provided with a drift layer having the first conductivity type; a well region having a second conductivity type; source regions having the first conductivity type; gate insulating layers in gate trenches penetrating the source regions and the well region and including a high-x material; gate electrodes on the gate insulating layers and including a metal material; a gate bus line connected to ends of the gate electrodes; a gate pad spaced apart from the gate bus line; a connector electrically connecting the gate bus line to the gate pad and including a material having a resistivity greater than those of the gate bus line and the gate pad; a dielectric layer on the gate electrodes, the gate bus line, the gate pad, and the connector; and a drain electrode on a lower surface of the substrate.