SiC Trench MOSFET Gate Routing Around Trench Intersection Corners
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Solution Overview
Problem
The reliability of the gate insulating layer in trench gate vertical MOSFETs is compromised when the gate lead-out layer crosses the corners where the gate trenches intersect, leading to increased on-resistance and reduced performance.
Innovation Solution
The design incorporates trench structures where the lengths of the connection trenches are set to twice the cell pitch, preventing the gate lead-out layer from crossing these intersections, thereby enhancing the reliability of the gate insulating layer and reducing on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate lead-out layer is allowed to cross the corners where gate trenches intersect to simplify the structure, then the manufacturing process is easier, but the reliability of the gate insulating layer deteriorates
Solution Approach 1:
The gate lead-out layer is extracted from the corner regions where trenches intersect. By preventing the gate lead-out layer from crossing these corners, the harmful interaction between the lead-out layer and the corner structures is eliminated, thus improving gate insulating layer reliability while maintaining manufacturing simplicity through alternative routing paths.
2Manufacturing precision
If the cell pitch is reduced to increase channel area per unit area, then the on-resistance is reduced, but the gate insulating layer reliability at trench intersections deteriorates
Solution Approach 1:
The gate lead-out layer is extracted from the critical corner regions even as cell pitch is reduced. This allows the cell pitch to be minimized for lower on-resistance while the gate lead-out layer follows a safe path that avoids the high-stress corner regions, preserving gate insulating layer reliability.
3Area of stationary object
If the gate lead-out layer crosses trench intersections to maintain compact design, then the device area is reduced, but the gate insulating layer reliability deteriorates due to increased stress at corners
Solution Approach 1:
The gate lead-out layer is extracted from the corner regions where trenches intersect. This separation prevents the lead-out layer from introducing additional stress at the already vulnerable corner regions, thereby maintaining gate insulating layer reliability while the overall device area remains compact through optimized trench arrangement.
Data Source
AI summary
A semiconductor device of embodiments includes: a silicon carbide layer having a first face parallel to a first direction and a second direction crossing the first direction and a second face facing the first face; a first trench on a side of the first face extending in the first direction; a second trench extending in the first direction; a third trench extending in the second direction and continuous with the first trench and the second trench; a fourth trench extending in the first direction, disposed between the first trench and the second trench, and spaced from the third trench in the first direction; a gate electrode in the first to fourth trench; a gate insulating layer; a first conductive layer crossing the third trench and connected to the gate electrode; a first electrode disposed on the first face; and a second electrode disposed on the second face.