SiC Gate Wiring Layout for Gate Oxide Breakdown Suppression
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Solution Overview
Problem
Conventional silicon carbide semiconductor devices experience dielectric breakdown of the gate insulating film during switching transitions due to high electric fields and displacement currents, especially at low temperatures, leading to reduced reliability and operational limitations.
Innovation Solution
The semiconductor device incorporates a design with a gate polysilicon wiring layer extending beyond the inner peripheral end of the field oxide film, forming a thinner insulating layer portion closer to the chip center, and sets the distance from the drop of the insulating layer to the contact holes to 21 μm or less, reducing voltage drops and electric field strength across p-type regions, thereby suppressing dielectric breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate insulating film is extended to the edge termination region with a thick field oxide film, then the electric field is reduced and dielectric breakdown is prevented, but the voltage drops across p-type regions increase and operational reliability deteriorates
Solution Approach 1:
The patent applies local quality by creating different insulating layer configurations in different regions: a thin insulating layer (gate insulating film only) in the active region for low voltage drop, and a thick insulating layer (gate insulating film + field oxide film) in the edge termination region for dielectric breakdown prevention. The gate polysilicon wiring layer is selectively positioned to face p-type regions only in the active region, providing localized electric field management.
Solution Approach 2:
The patent segments the insulating layer into two distinct parts: the gate insulating film that extends across the entire device, and the field oxide film that is selectively positioned only in the edge termination region. This segmentation allows each layer to serve its specific function - the gate insulating film provides continuous coverage while the field oxide film provides localized electric field reduction where needed.
2Reliability
If the distance from the drop of the insulating layer to the contact holes is increased, then the electric field strength is reduced, but the voltage drops across p-type regions increase
Solution Approach 1:
The patent solves the distance contradiction by transitioning from a one-dimensional distance parameter to a two-dimensional spatial configuration. Instead of uniformly increasing the distance from the insulating layer drop to contact holes, the patent positions the gate polysilicon wiring layer to face specific p-type regions in the active region, creating a targeted three-dimensional electric field management structure that reduces voltage drops while maintaining dielectric breakdown suppression.
3Reliability
If the gate polysilicon wiring layer is positioned closer to the active region, then the electric field control is improved, but the insulating layer thickness is reduced and dielectric breakdown risk increases
Solution Approach 1:
The patent resolves this contradiction by applying local quality - the gate polysilicon wiring layer is positioned to face p-type regions selectively in the active region where low voltage drop is needed, while the field oxide film provides thick insulating coverage in the edge termination region where dielectric breakdown prevention is the priority. This localized positioning allows each region to optimize for its specific requirement.
Data Source
AI summary
In an intermediate region between an active region and an edge termination region, on a front surface of a semiconductor substrate, a gate polysilicon wiring layer is provided via an insulating layer in which a gate insulating film and a field oxide film are stacked sequentially. An inner peripheral end of the field oxide film is positioned directly beneath the gate polysilicon wiring layer, which extends inward from the field oxide film and terminates on the gate insulating film. At the surface of the insulating layer directly beneath the gate polysilicon wiring layer, on the inner peripheral end of the field oxide film, a drop is formed by a difference in thickness due to whether the field oxide film is present. A distance from the drop to a contact hole of the active region is 21 μm or less.