SiC Device Gate Wiring Segmentation for Resistance Uniformity
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Solution Overview
Problem
Conventional silicon carbide semiconductor devices face challenges in reducing in-plane variation of gate resistance, leading to decreased switching speed and potential current concentration during high-speed operations due to localized high gate resistance in the cell region.
Innovation Solution
The silicon carbide semiconductor device incorporates a silicon carbide semiconductor substrate with an active region and a termination region, featuring a gate global wiring line that encircles source pads and is split at substrate corners, along with source connections that connect the outer periphery source wiring line to source pads, thereby reducing gate resistance variation and enhancing switching performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate wiring structure is used in the cell region, then the device structure is simple, but the in-plane variation of gate resistance increases leading to localized high resistance areas
Solution Approach 1:
The gate wiring line is segmented into multiple portions (first portion, second portion, third portion) that are split at substrate corners. This segmentation allows the gate wiring to be distributed more uniformly across the cell region, reducing in-plane variation of gate resistance by eliminating localized high resistance areas that would occur with a conventional continuous wiring structure.
2Speed
If the gate global wiring line is continuous without splitting, then the wiring structure is simple, but switching speed decreases due to current concentration and high gate resistance in certain regions
Solution Approach 1:
The gate global wiring line is split into multiple portions at substrate corners, creating a more distributed wiring configuration. This segmentation reduces gate resistance variation across the cell region, enabling faster and more uniform switching speed across all unit cells by preventing current concentration in specific high-resistance areas.
Solution Approach 2:
The wiring line configuration is optimized locally at substrate corners where splits occur. This local modification of the wiring structure addresses the specific problem of high gate resistance at corner regions, improving switching speed in those critical areas without requiring complete redesign of the entire wiring system.
3Reliability
If avalanche current flows through the outer periphery source wiring line, then the wiring structure is simple, but wire deterioration occurs and reliability decreases
Solution Approach 1:
The harmful effect of avalanche current on the outer periphery source wiring line is eliminated by extracting the avalanche current path from the wiring line. The configuration allows avalanche current to flow directly into source pads without traversing the outer periphery source wiring line, thereby preventing wire deterioration and improving reliability.
4Productivity
If source pads are not encircled by the gate global wiring line, then the wiring structure is simpler, but gate resistance variation increases and switching performance deteriorates
Solution Approach 1:
The gate global wiring line is configured to encircle source pads in the active region, creating a localized optimization of the wiring structure. This encirclement configuration improves gate resistance uniformity and switching performance in the critical active region where unit cells are located, without requiring the wiring to encircle the entire device perimeter.
Data Source
AI summary
A silicon carbide semiconductor device includes an upper gate electrode including a gate pad and a gate wiring line, and an upper source electrode including first and second source pads. The gate wiring line includes a gate global wiring line extending to encircle the source pads, and a gate connection wiring line. The upper source electrode includes an outer periphery source wiring line extending to encircle the gate global wiring line, and first and second source connections connecting the outer periphery source wiring line to the first and second source pads, respectively. The gate global wiring line includes a first portion, a second portion, and a third portion. The first portion is split at a first substrate corner and a second substrate corner and lies between the first substrate corner and the second substrate corner.