SiC Vertical Transistor Groove Source Contact Resistance
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Solution Overview
Problem
In silicon carbide semiconductor devices, the partial removal of the n-type layer during manufacturing leads to a decrease in impurity concentration at the source electrode contact area, resulting in increased contact resistance and reduced current flow.
Innovation Solution
The silicon carbide semiconductor device design includes a second area deeper than the first area, where the impurity element is doped, to maintain high impurity concentration and reduce contact resistance without significant design changes, featuring a source electrode in contact with the second area and a groove structure with a sidewall, allowing for continuous impurity doping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the n-type layer is partially removed during manufacturing, then the device structure is formed, but the impurity concentration at the source electrode contact area decreases
Solution Approach 1:
The patent applies preliminary action by forming the second area deeper than the first area before the partial removal of the n-type layer. This pre-positioning ensures that when the n-type layer is removed to form the groove structure, the source electrode can still contact the high impurity concentration region at the deeper second area, thus maintaining impurity concentration despite the manufacturing step.
2Device complexity
If the n-type layer is partially removed to form groove structure, then device architecture is achieved, but contact resistance increases
Solution Approach 1:
The patent applies local quality by creating a second area with different depth characteristics compared to the first area. The second area is positioned deeper and maintains high impurity concentration specifically at the source electrode contact region, while other areas can have different properties. This localized differentiation ensures low contact resistance at the critical contact point while allowing the groove structure to exist elsewhere.
3Manufacturing precision
If the second area is positioned deeper than the first area, then impurity concentration is maintained, but device structure becomes more complex
Solution Approach 1:
The patent applies dimensionality change by utilizing the depth dimension to solve the impurity concentration problem. Instead of trying to maintain uniform depth across all areas, the solution creates a vertical differentiation where the second area extends deeper than the first area. This depth-based differentiation allows the source electrode to contact the high impurity concentration region while maintaining the necessary groove structure for device operation.
Data Source
AI summary
A silicon carbide semiconductor device to be a vertical transistor includes: a silicon carbide semiconductor first layer 21 of a first conductivity type; a silicon carbide semiconductor second layer 22 of a second conductivity type that is different from the first conductivity type on the first layer 21; a silicon carbide semiconductor third layer 120 of the first conductivity type on the second layer 22; and a groove 30 having a sidewall 30a at portions of the third layer 120, the second layer 22, and the first layer 21, wherein the third layer 120 has a first area 121 facing the sidewall 30a of the groove 30 and a second area 122 further away from the sidewall 30a of the groove 30 than the first area 121, wherein the second area 122 and the first area 121 are continuous, and wherein the second area 122 is provided deeper than the first area 121 from a surface side of the third layer 130 toward the first layer 21.