SiC Semiconductor Device Guard Ring Recess Structure
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Solution Overview
Problem
The existing semiconductor devices using silicon carbide (SiC) face challenges with electric field concentration and dielectric breakdown due to high voltage applications, particularly in the corner portions of recess structures, leading to reduced yield and increased costs, as they require multiple masking steps and impurity diffusion issues.
Innovation Solution
A method involving a single mask process to form a recess structure with a taper shape and impurity injection, ensuring the corner portions are covered with a guard ring or FLR injection layer, reducing electric field concentration and enhancing withstand voltage characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple masking steps are used to form guard ring and JTE structures with different impurity concentrations, then the withstand voltage characteristic is improved, but the manufacturing complexity and number of steps increase
Solution Approach 1:
The patent combines the guard ring and JTE structures into a single impurity diffusion layer formed by one masking step. The key insight is that in SiC devices, impurities are activated without significant diffusion, allowing a single impurity layer to serve both functions: the inner region acts as guard ring while the outer region acts as JTE, eliminating the need for separate masking steps while maintaining the dual-functionality required for high withstand voltage
Solution Approach 2:
The single impurity diffusion layer is designed to perform multiple functions simultaneously. By carefully controlling the impurity concentration profile within one layer, the structure provides both guard ring functionality (inner high-concentration region) and JTE functionality (outer lower-concentration region), making one structure serve where traditionally two separate structures were needed
2Productivity
If a single mask process is used to simplify manufacturing, then the number of steps is reduced, but the impurity concentration cannot be optimized for both guard ring and JTE regions
Solution Approach 1:
The patent applies local quality by creating different impurity concentration regions within a single diffusion layer. The inner region (guard ring) has higher impurity concentration while the outer region (JTE) has lower concentration, achieved through controlled impurity diffusion from a single mask. This allows each region to have the specific concentration characteristics it needs while using only one masking step
Solution Approach 2:
The patent utilizes parameter changes in the impurity diffusion process to achieve different concentration profiles from a single mask. By controlling diffusion time, temperature, and impurity source characteristics, the process creates a gradient where the inner region receives higher impurity concentration than the outer region, enabling both guard ring and JTE functions with optimized concentrations
3Reliability
If high impurity concentration is used in the guard ring to ensure withstand voltage, then the withstand voltage characteristic is improved, but electric field concentration occurs in corner portions of recess structures
Solution Approach 1:
The patent addresses the corner field concentration problem by extending the impurity diffusion layer onto the side surfaces of the recess structure. This three-dimensional coverage ensures that corner portions, which are geometrically prone to field concentration, are also covered by the impurity layer. The solution moves from a two-dimensional planar coverage to a three-dimensional coverage that includes vertical surfaces, eliminating the harmful corner effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes the withstand voltage in SiC semiconductor devices by effectively covering corner portions with impurity layers, preventing dielectric breakdown and reducing the number of masking steps, thereby improving yield and cost-effectiveness.
Implementation Method 1
forming an impurity layer of a second conductivity type in a recess bottom surface and a recess side surface in the recess structure by impurity injection through the resist pattern
Data Source
AI summary
A semiconductor device capable of suppressing generation of a high electric field and preventing a dielectric breakdown from occurring, and a method of manufacturing the same. The method of manufacturing a semiconductor device includes (a) preparing an n+ substrate to be a ground constituted by a silicon carbide semiconductor of a first conductivity type, (b) forming a recess structure surrounding an element region on the n+ substrate by using a resist pattern, and (d) forming a guard ring injection layer to be an impurity layer of a second conductivity type in a recess bottom surface and a recess side surface in the recess structure by impurity injection through the resist pattern, and a corner portion of the recess structure is covered with the impurity layer.