Si/SiC Heterojunction MOSFET Structure for Stable Gate Oxide
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Solution Overview
Problem
Power MOSFETs formed from silicon carbide (SiC) suffer from low channel mobility, gate oxide instability, and significant voltage drop losses at the Si/SiC interface due to bandgap differences, necessitating higher gate voltages and modified drivers.
Innovation Solution
A vertical power MOSFET structure with a Si/SiC heterojunction interface, where the gate oxide is formed in the Si layer, and a thin, highly doped N-type layer in SiC reduces rectification and enhances tunneling current, utilizing SiC's advantages while minimizing carbon-related issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If SiC is used to form power MOSFETs, then breakdown voltage and temperature stability are improved, but channel mobility decreases and gate oxide stability deteriorates
Solution Approach 1:
The device is segmented into two distinct semiconductor regions: a SiC drift region for high voltage blocking and a Si gate region for low-resistance channel formation. This segmentation allows each material to be used in its optimal application, resolving the contradiction between high breakdown voltage (achieved in SiC) and gate oxide stability (achieved in Si).
Solution Approach 2:
A thin highly doped N-type SiC layer is introduced as an intermediary between the Si gate and the main SiC drift region. This intermediate layer facilitates carrier transport while protecting the gate oxide from carbon-related degradation, enabling both high breakdown voltage and gate oxide stability.
2Stability of the object's composition
If SiC is used to form power MOSFETs, then temperature stability is improved, but channel mobility decreases requiring higher gate voltages
Solution Approach 1:
The MOSFET channel is formed in the Si region rather than SiC, where Si provides superior carrier mobility. This segmentation enables easier device operation with standard gate voltages (5V-10V) while the SiC drift region maintains temperature stability for high-voltage blocking.
3Adaptability or versatility
If Si and SiC layers are bonded together at an Si/SiC interface, then the benefits of both materials are utilized, but voltage drop losses occur at the interface due to bandgap differences
Solution Approach 1:
The doping concentration in the intermediate N-type SiC layer is dramatically increased (e.g., >10^19 atoms/cm³) compared to the drift region. This parameter change reduces the depletion width and barrier height at the Si/SiC interface, minimizing voltage drop losses while maintaining the heterojunction benefits.
4Volume of moving object
If SiC is used to form power MOSFETs, then device size is reduced, but carbon at the gate oxide interface causes reliability issues
Solution Approach 1:
The gate oxide formation process is extracted from the SiC region and relocated to the Si region. By forming the gate oxide in Si rather than at the SiC interface, carbon contamination is eliminated from the gate oxide formation process, ensuring high reliability while maintaining the compact SiC-based device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure achieves higher breakdown voltage, lower specific on-resistance, improved thermal conductivity, and reliable gate drive with reduced voltage drop and enhanced electron mobility, addressing the limitations of SiC-based MOSFETs.
Implementation Method 1
a thin, highly doped N-type layer in SiC reduces rectification and enhances tunneling current
Implementation Method 2
The trenches are oxidized to form a gate oxide
Implementation Method 3
Si has a bandgap that is narrower than that of SiC. As a result, at the interface there is rectification
Data Source
AI summary
Trench-gate MOSFETs use a N+ SiC substrate with a N SiC drift layer. A Si wafer is bonded to the top of the SiC wafer, forming a Si/SiC heterojunction at the interface. Gate trenches are formed in the Si layer, oxidized, and filled with a conductor. Since the gate oxide is only in contact with the Si, and not the SiC, there is no problem with carbon at the gate oxide interface. Also, since the MOSFET is formed in the Si layer, electron mobility near the gates is high. JFET channel regions in the SiC layer pinch off during short circuit, high current conditions to limit drain current and thus achieve a higher short circuit withstand time capability. At the Si/SiC interface, a thin, highly doped n-type layer is formed in the SiC layer that allows tunneling current flowing through the barrier to lower the voltage drop across the heterojunction.