SiC Semiconductor Device Hetero-Layer Dry Etching
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Solution Overview
Problem
Conventional methods for manufacturing semiconductor devices using silicon carbide epitaxial layers suffer from etching damage and increased device size due to isotropic wet etching, which hinders miniaturization and increases on-resistance.
Innovation Solution
The method involves forming a first hetero-semiconductor layer on a semiconductor substrate, followed by an etching stopper layer, and then a second hetero-semiconductor layer, using dry etching with a selective etching gas to minimize plasma damage and subsequent thermal oxidation to control layer thickness, allowing for precise etching and miniaturization without the need for wet etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wet etching is used to remove the hetero-semiconductor layer, then the etching process is simple, but etching damage occurs and device size increases due to isotropic etching
Solution Approach 1:
The patent replaces wet etching (chemical/mechanical process) with dry etching (plasma-based physical-chemical process). This substitution eliminates the isotropic etching characteristics of wet etching that cause device size increase, while maintaining manufacturing feasibility through controlled plasma etching processes that achieve both precision and damage reduction.
Solution Approach 2:
The patent changes the etching parameters by switching from liquid-based wet etching to gas-based dry etching. This parameter change transforms the etching mechanism from isotropic to anisotropic, enabling precise depth control and minimizing lateral etching that increases device size, while the plasma parameters can be optimized to reduce plasma damage.
2Ease of manufacture
If wet etching is used to remove the hetero-semiconductor layer, then the etching process is simple, but plasma damage increases
Solution Approach 1:
The patent optimizes plasma etching parameters including gas composition, power density, pressure, and temperature to minimize plasma damage. By carefully controlling these parameters, the etching process achieves high precision while reducing the harmful effects of plasma exposure on the semiconductor structures.
Solution Approach 2:
The patent introduces a gate insulating film as an intermediary layer between the gate electrode and the hetero-semiconductor layer. This intermediary protects sensitive regions from direct plasma damage during the dry etching process, while still allowing the etching to proceed effectively in the target regions.
3Volume of moving object
If the hetero-semiconductor region is miniaturized, then device size decreases, but on-resistance increases
Solution Approach 1:
The patent applies local quality by creating a hetero-joined structure where the hetero-semiconductor layer is selectively positioned and dimensioned. The layer thickness and material composition are optimized locally at the junction region to maintain low on-resistance despite overall device miniaturization, achieving both small size and low resistance through spatially differentiated properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses plasma damage and allows for the miniaturization of semiconductor devices, reducing on-resistance and enhancing the controllability and yield of the manufacturing process while maintaining high voltage resistance.
Implementation Method 1
forming an etching stopper layer at a predetermined position on a first surface of the first hetero-semiconductor layer opposite the semiconductor substrate, the etching stopper layer including a material having a different etching rate from that of the first hetero-semiconductor material
Implementation Method 2
thermally oxidizing the first hetero-semiconductor layer
Implementation Method 3
using dry etching with a selective etching gas to minimize plasma damage
Data Source
AI summary
A method for producing a semiconductor device includes forming a first hetero-semiconductor layer as a hetero-junction to a surface of a silicon carbide epitaxial layer. This layer is composed of polycrystalline silicon having a band gap different from that of the silicon carbide epitaxial layer. An etching stopper layer composed of a material having a different etching rate from that of the polycrystalline silicon is formed on the surface of the first hetero-semiconductor layer. A second hetero-semiconductor layer composed of polycrystalline silicon is formed so that the second hetero-semiconductor layer contacts the surface of the first hetero-semiconductor layer and the etching stopper layer. The etching stopper layer is removed, the first hetero-semiconductor layer is thermally oxidized, and the thermally oxidized portion is then removed.