SiC IGFET Gate Oxide Layout for Low Resistance and Breakdown Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
MOSFET devices face challenges in reducing on-resistance while avoiding punch through breakdown and maintaining high operating voltage, which can lead to increased gate oxide electric fields and reduced device reliability.
Innovation Solution
An insulating gate field-effect transistor (IGFET) device with a silicon carbide semiconductor body, featuring doped well regions and a gate oxide with distinct thickness dimensions, where the interior section is at least five times thicker than the outer section, is designed to reduce electric fields and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the FET channel is reduced to decrease on-resistance, then power dissipation losses are reduced, but punch through breakdown occurs
Solution Approach 1:
The gate oxide structure implements local quality by having different thicknesses in different regions: a thinner outer section for optimal electrical performance and a thicker interior section for reliability. This localized variation in oxide thickness allows the device to achieve low on-resistance while preventing punch-through breakdown through the enhanced blocking capability in the center region.
2Reliability
If dopant concentration of well regions is increased to reduce punch through, then reliability is improved, but voltage needed to switch device increases
Solution Approach 1:
The gate oxide thickness is locally optimized with a thinner outer section that allows for lower switching voltages while the thicker interior section provides the necessary blocking capability to prevent punch-through, thereby resolving the contradiction between switching efficiency and reliability.
3Reliability
If gate oxide thickness is increased to reduce electric field, then device reliability is improved, but on-resistance increases
Solution Approach 1:
The gate oxide is designed with spatially varying thickness where the outer sections are thinner to maintain low on-resistance and the interior section is thicker to reduce electric field strength and prevent breakdown. This local differentiation allows simultaneous optimization of both conductivity and reliability.
Solution Approach 2:
The gate oxide is segmented into distinct thickness regions - outer sections with smaller thickness and an interior section with larger thickness. This segmentation allows each region to perform its specialized function: the outer regions minimize resistance while the interior region minimizes electric field stress.
4Loss of energy
If gate oxide thickness is reduced to maintain low on-resistance, then power losses are reduced, but electric field strength increases causing breakdown
Solution Approach 1:
The gate oxide thickness is locally optimized with thinner outer sections for low resistance and thicker interior section for electric field management, allowing the device to achieve low power losses while maintaining high reliability through spatially differentiated functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The IGFET device effectively decreases electric fields in the gate oxide, thereby increasing the reliability and lifespan of the device while maintaining low on-resistance and high operating voltage capabilities.
Implementation Method 1
The ratio of dielectric constants between the semiconductor and the gate oxide will amplify the electric field strength component normal to the surface [e.g. Eox = (εSiC / εox) ∗Esic], by the ratios of the relative permittivities. As the electric fields generated in the gate oxide increase, the reliability and/or useful life of the MOSFET device can decrease due to breakdown in the gate oxide material.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
An insulated gate field-effect transistor (IGFET) device includes a semiconductor body (200) and a gate oxide (234). The semiconductor body includes a first well region (216) doped with a first type of dopant and a second well region (220) that is doped with an opposite, second type of dopant and is located within the first well region. The gate oxide includes a relatively thinner outer section (244) and a relatively thicker interior section (246). The outer section is disposed over the first well region and the second well region. The interior section is disposed over a junction gate field effect transistor region (218) of the semiconductor body doped with the second type of dopant. A conductive channel is formed through the second well region when a gate signal is applied to a gate contact (250) disposed on the gate oxide.