SiC Bonded Substrate Interface Doping for Low Contact Resistance

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Solution Overview

Problem

When SiC single crystal and SiC polycrystal substrates are directly bonded, interface resistance increases, affecting device characteristics.

Innovation Solution

A method involving damaged layer formation, specific element introduction, and thermal treatment to reduce interface resistance by moving the specific element into the damaged layer, using pentavalent elements for N-type semiconductors and trivalent elements for P-type semiconductors, with elements like nitrogen, phosphorus, and aluminum.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If SiC single crystal and SiC polycrystal are directly bonded, then bonding process is simple, but interface resistance increases

Engineering Contradiction:
Improvebonding process complexityVSAvoidinterface resistance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

A damaged layer is formed on the bonding surface before bonding occurs, and specific elements are introduced in advance. This preliminary preparation enables the damaged layer to facilitate element diffusion and reduce interface resistance during subsequent bonding, resolving the contradiction between simple bonding process and low interface resistance

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

A damaged layer is introduced as an intermediary structure between the SiC single crystal and polycrystal substrates. This damaged layer serves as a mediator that enables controlled diffusion of specific elements (such as aluminum, boron, or gallium) to the bonding interface, thereby reducing interface resistance without complicating the overall bonding process

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If damaged layer formation and specific element introduction steps are added, then interface resistance is reduced, but manufacturing process complexity increases

Engineering Contradiction:
Improveinterface resistanceVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The damaged layer formation step and specific element introduction step are merged into a unified process sequence that occurs before bonding. By combining these functions in a coordinated manner, the patent reduces interface resistance while minimizing the increase in manufacturing process complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent utilizes thermal treatment to change the physical state and promote diffusion of specific elements into the damaged layer. By controlling temperature parameters during thermal treatment, the process achieves effective interface resistance reduction through controlled element diffusion, balancing improved reliability with manageable process complexity

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Prevents the occurrence of interface resistance at the bonded interface, enhancing device characteristics by reducing the energy barrier and enabling electron tunneling.

Implementation Method 1

a thermal treatment step for subjecting the bonded semiconductor substrate to a thermal treatment, in which the thermal treatment step is a step of causing the specific element introduced into at least one of the first semiconductor substrate and the second semiconductor substrate to move into the damaged layer

Methodology Applied
Scientific EffectDiffusion: Diffusion

Implementation Method 2

The damaged layer formation step may be a step of forming the damaged layer by performing at least one treatment of ion implantation, neutral element implantation, and plasma irradiation

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentEP4583148A1Semiconductor substrate and method for manufacturing semiconductor substrate
Publication Date: 2025.07.09 SUMITOMO METAL MINING CO LTD
  • EP4583148A1 patent drawingFigure 1
  • EP4583148A1 patent drawingFigure 2~4
  • EP4583148A1 patent drawingFigure 5

AI summary

Provided are a semiconductor substrate capable of preventing occurrence of interface resistance at a bonded interface, and a method for manufacturing a semiconductor substrate. A method for manufacturing a semiconductor substrate includes: a damaged layer formation step of forming a damaged layer in at least one of a first bonding target surface of a first semiconductor substrate and a second bonding target surface of a second semiconductor substrate; a specific element introduction step of introducing a specific element into at least one of the first bonding target surface and the second bonding target surface; a bonding step of bonding the first bonding target surface and the second bonding target surface together to form a bonded semiconductor substrate having a bonded interface; and a thermal treatment step of subjecting the bonded semiconductor substrate to a thermal treatment, in which the thermal treatment step is a step of causing the specific element introduced into at least one of the first semiconductor substrate and the second semiconductor substrate to move into the damaged layer.