SiC JFET Channel Definition Using Sacrificial Layers
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Solution Overview
Problem
Existing silicon carbide power transistors face high impedance due to imprecise definition of channel length, which is not effectively addressed by current manufacturing methods, and the use of multiple photomasks increases costs.
Innovation Solution
A manufacturing method that utilizes a single photolithography process combined with controlled wet etching and sacrificial layers to precisely define channel length, reducing impedance and minimizing photomask usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photomasks are used to define channel length, then manufacturing precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent introduces a sacrificial layer as an intermediary substance that enables precise channel length definition without requiring multiple photomasks. The sacrificial layer is deposited over the base region, patterned once to define the channel length, and then selectively removed to create the desired structure. This intermediary approach replaces the need for multiple photomasking steps while maintaining manufacturing precision.
Solution Approach 2:
The sacrificial layer is deposited and patterned in advance before the actual device structure is formed. This preliminary action establishes the precise channel length definition early in the manufacturing process, eliminating the need for subsequent photomasking steps and reducing overall process complexity.
2Manufacturing precision
If conventional manufacturing methods are used, then process simplicity is maintained, but impedance remains high due to imprecise channel length definition
Solution Approach 1:
The sacrificial layer serves as a mediator that simplifies the manufacturing process while achieving precise channel length definition. By using this temporary structure, the method avoids the complexity of multiple photomasks and aligns with silicon carbide material characteristics, making the process easier to manufacture with higher precision.
Solution Approach 2:
The patent changes the manufacturing approach by introducing a sacrificial layer deposition step that allows for precise dimensional control. This parameter change in the manufacturing process enables accurate channel length definition through controlled deposition thickness and single-step patterning, improving precision while maintaining ease of manufacture.
3Reliability
If channel length is not precisely defined, then manufacturing process is simpler, but impedance increases reducing device performance
Solution Approach 1:
The sacrificial layer acts as a mediator that enables precise channel length definition to improve device reliability and performance. This intermediary structure allows for accurate control of the channel region, which directly impacts impedance and overall device performance, while keeping the manufacturing process relatively simple through single-step patterning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves precise channel length definition, reducing impedance and costs by using sacrificial layers and controlled etching processes, thereby enhancing the performance and cost-effectiveness of silicon carbide power transistors.
Implementation Method 1
utilizes a single photolithography process combined with the time control of a wet etching process
Data Source
AI summary
A manufacturing method of a semiconductor device includes the following steps. A base region is formed in a substrate. A protective layer is formed on the substrate and covers the base region. First and second sacrificial layers are formed on the substrate and cover the protective layer. A source region, a well region, and a junction field effect transistor (JFET) region are formed in the substrate. When the source region, the well region, and the JFET region are formed in sequence, the source region and the well region are formed by the first sacrificial layer, and the JFET region is formed by the second sacrificial layer. When the JFET region, the well region, and the source region are formed in sequence, the JFET region is formed by the first sacrificial layer, and the well region and the source region are formed by the second sacrificial layer.