SiC Trench Gate Structure With JFET Defects for On-Voltage Suppression

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Silicon carbide (SiC) semiconductor devices with trench gate structures face increased on-voltage due to basal plane dislocation expansion to stacking faults during reverse conduction, as holes reach and expand basal plane dislocations, affecting element operation.

Innovation Solution

The SiC semiconductor device incorporates defect portions in the JFET portion to trap carriers, preventing them from reaching basal plane dislocations and thus suppressing the expansion to stacking faults, which includes a substrate with a specific impurity concentration gradient and trench gate structure, allowing the parasitic diode to function as a freewheeling diode without a separate component.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a trench gate structure is formed in a SiC semiconductor device, then the switching performance is improved, but the on-voltage increases due to basal plane dislocations expanding to stacking faults during reverse conduction

Engineering Contradiction:

Improveswitching performanceVSAvoidon-voltage increase

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent converts the harmful effect of basal plane dislocations into a beneficial feature by intentionally forming stacking faults in a controlled manner. These stacking faults act as carrier trapping regions that prevent holes from reaching the trench gate structure during reverse conduction, thereby preventing the on-voltage increase while maintaining the switching performance benefits of the trench gate structure.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent introduces stacking faults as an intermediary layer between the basal plane dislocations and the trench gate structure. This intermediary stacking fault layer traps carriers (holes) and prevents them from directly interacting with the trench gate, thereby eliminating the harmful effect of on-voltage increase while preserving the beneficial switching characteristics.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Object-generated harmful factors

If defect portions are formed in the JFET portion to trap holes, then on-voltage increase is suppressed, but the device complexity increases

Engineering Contradiction:

Improveon-voltage suppressionVSAvoidstructure complexity

Core Design Contradiction:

Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent merges the formation of stacking faults with the existing JFET portion structure. The stacking faults are formed within the n-type buffer layer in the JFET region, combining the carrier trapping function with the existing current conduction path, thereby achieving on-voltage suppression without significantly increasing device complexity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent changes the physical parameters of the buffer layer by controlling the formation of stacking faults through specific crystal orientation and growth conditions. By adjusting the stacking fault density and distribution parameters, the patent achieves effective hole trapping while maintaining a relatively simple device structure.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively reduces on-voltage by trapping holes and preventing basal plane dislocation expansion to stacking faults, enhancing the operational efficiency of the SiC semiconductor device and simplifying the inverter circuit configuration by utilizing the parasitic diode as a freewheeling diode.

Implementation Method 1

The JFET portion is formed with defect portions. The defect portions trap carriers, such as holes, to prevent the carriers from reaching defects, such as basal plane dislocations

Methodology Applied

Scientific EffectCarrier trapping: Absorption (physical)

Implementation Method 2

utilizing a parasitic diode for freewheeling

Methodology Applied

Scientific EffectDiode conduction: Diode

Data Source

PatentUS20230378292A1Silicon carbide semiconductor device, inverter circuit using the same, and method for manufacturing silicon carbide semiconductor device

Publication Date: 2023.11.23 DENSO CORP

AI summary

A SiC semiconductor device includes a substrate of a first conductivity type, a buffer layer of the first conductivity type on the substrate, a low-concentration layer on the buffer layer, a first deep layer and a JFET portion on the low-concentration layer, a current diffusion layer of the first conductivity type disposed on the JFET portion and having an impurity concentration higher than the low-concentration layer, a second deep layer of a second conductivity type disposed on the first deep layer, a base layer of the second conductivity type disposed on the current diffusion layer and the second deep layer, an impurity region of the first conductivity type disposed in a surface layer portion of the base layer, and a trench gate structure penetrating the impurity region and the base layer and reach the current diffusion layer. The JFET portion is formed with defect portions.