SiC JFET Epitaxial Structure Without Deep Trench Etching
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Solution Overview
Problem
The manufacturing of silicon carbide (SiC) JFETs faces challenges due to the difficulty of deep trench etching and crystal damage during the process, which affects device performance, and existing unipolar devices have high on-resistance and limited voltage operation.
Innovation Solution
A manufacturing method involving a substrate with a mask layer and selective growth of semiconductor epitaxial layers, where the mask layer is used to avoid deep trench etching and ion implantation is performed to reduce on-resistance, forming a PN junction for improved breakdown voltage and energy conversion efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If deep trench etching is performed on silicon carbide to manufacture JFETs, then the device structure can be formed, but the etching process causes crystal damage and affects device performance
Solution Approach 1:
Instead of etching trenches into the silicon carbide substrate to form the JFET structure, the patent inverts the approach by selectively growing epitaxial layers on the substrate surface. The mask layer defines the device regions, and epitaxial growth builds the structure upward rather than etching downward, thereby avoiding crystal damage from deep trench etching while still forming the required JFET structure with source, drain, and gate regions
Solution Approach 2:
The patent introduces a mask layer as an intermediary element that patterns the substrate surface before epitaxial growth. This mask layer serves as a template that defines where semiconductor epitaxial layers will grow, eliminating the need for post-growth trench etching and associated crystal damage while maintaining precise device structure formation
2Reliability
If unipolar devices are designed for high voltage operation, then the on-resistance becomes very large, but if bipolar devices are used for high voltage, then switching loss increases and switching frequency decreases
Solution Approach 1:
The patent employs ion implantation to precisely control the doping concentration and conductivity type of the semiconductor epitaxial layers. By adjusting doping parameters during ion implantation, the device achieves optimized electrical characteristics that enable high voltage operation with reduced on-resistance, resolving the trade-off between voltage handling capability and energy loss in unipolar devices
3Loss of energy
If the drift layer thickness is reduced to lower on-resistance in silicon carbide devices, then the breakdown voltage capability is compromised, but if thickness is increased, then the on-resistance increases
Solution Approach 1:
The patent creates different conductivity types in different regions of the semiconductor structure through selective ion implantation. The drift region maintains appropriate thickness for breakdown voltage while adjacent regions are doped with opposite conductivity types to form field effect structures that modulate carrier concentration locally, thereby reducing on-resistance without compromising the drift layer's voltage blocking capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the manufacturing process, reduces etching damage, and enhances the crystal quality of SiC epitaxial layers, resulting in lower on-resistance and increased breakdown voltage, improving the performance and energy conversion efficiency of SiC unipolar devices.
Implementation Method 1
by using the mask layer as a mask, selectively growing a first semiconductor epitaxial layer at the opening
Implementation Method 2
performing ion implantation to the second semiconductor epitaxial layer to form a third semiconductor epitaxial layer
Data Source
AI summary
This disclosure provides a method for manufacturing a semiconductor structure, which includes: providing a substrate, forming a mask layer on the substrate, where the mask layer is provided with an opening exposing the substrate; by using the mask layer as a mask, selectively growing a first semiconductor epitaxial layer at the opening, where the first semiconductor epitaxial layer does not cover a surface of the mask layer away from the substrate; removing mask layer, and forming a second semiconductor epitaxial layer on the substrate and the first semiconductor epitaxial layer by performing secondary epitaxy; where the second semiconductor epitaxial layer covers a surface of the first semiconductor epitaxial layer away from the substrate, and a conductivity type of the second semiconductor epitaxial layer is opposite to a conductivity type of the first semiconductor epitaxial layer; performing ion implantation to the second semiconductor epitaxial layer to form a third semiconductor epitaxial layer, where the third semiconductor epitaxial layer is located on a side of the first semiconductor epitaxial layer away from the substrate, the third semiconductor epitaxial layer is connected to the first semiconductor epitaxial layer, and a conductivity type of the third semiconductor epitaxial layer is same as the conductivity type of the first semiconductor epitaxial layer.