SiC JFET Gate Segmentation for On-Resistance Reduction
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Solution Overview
Problem
The existing junction field effect transistors (JFETs) using silicon carbide substrates face challenges in reducing on-resistance due to direct contact between high concentration gate regions and channel regions, leading to increased depletion layer extension and higher on-resistance.
Innovation Solution
Incorporating a counter doped region between the gate and channel regions, with the high concentration gate region included within the low concentration gate region, and forming the high concentration gate region at a shallower depth to prevent direct contact with the channel, thereby reducing the depletion layer extension and on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high concentration gate region is formed to improve gate control, then the gate control capability is improved, but the on-resistance increases due to depletion layer extension into the channel region
Solution Approach 1:
The gate region is divided into two distinct concentration zones: a low concentration gate region (10^18 to 10^19 atoms/cm³) adjacent to the channel region and a high concentration gate region (10^19 to 10^20 atoms/cm³) positioned deeper in the substrate. This segmentation allows the low concentration region to minimize depletion layer extension and on-resistance, while the high concentration region provides strong gate control capability for reliable device operation.
Solution Approach 2:
Different impurity concentrations are applied to different spatial locations within the gate region. The low concentration zone is positioned where it directly interfaces with the channel region to reduce depletion effects, while the high concentration zone is positioned deeper to provide strong electrostatic control. This local quality variation optimizes both on-resistance and gate control capability simultaneously.
2Length of stationary object
If the gate region impurity concentration is increased to reduce depletion layer width, then the depletion layer width is reduced, but the on-resistance increases due to direct contact with the channel region
Solution Approach 1:
The gate region is segmented into low and high concentration zones positioned at different depths. The low concentration zone (10^18 to 10^19 atoms/cm³) is positioned adjacent to the channel region where it directly influences the depletion layer width, minimizing its extension. The high concentration zone (10^19 to 10^20 atoms/cm³) is positioned deeper to provide overall gate control without directly increasing on-resistance.
Solution Approach 2:
The impurity concentration parameter is varied spatially within the gate region rather than being uniform. By changing the concentration from low (10^18 to 10^19 atoms/cm³) near the channel to high (10^19 to 10^20 atoms/cm³) deeper in the substrate, the patent optimizes both depletion layer width control and on-resistance characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the on-resistance and enhances the off-characteristics of the JFET by minimizing the depletion layer extension and improving current passage, resulting in better performance and reliability.
Implementation Method 1
direct contact between high concentration gate regions and channel regions, leading to increased depletion layer extension and higher on-resistance
Data Source
AI summary
A method of manufacturing a semiconductor device that includes a junction field effect transistor, the junction field effect transistor including a semiconductor substrate of a first conductivity type, an epitaxial layer of the first conductivity type formed on the semiconductor substrate, a source region of the first conductivity type formed on a surface of the epitaxial layer, a channel region of the first conductivity type formed in a lower layer of the source region, a pair of trenches formed in the epitaxial layer so as to sandwich the source region therebetween, and a pair of gate regions of a second conductivity type, opposite to the first conductivity type, formed below a bottom of the pair of trenches.